hvf/arm: expose FEAT_SME2 to guest if available
Starting from M4 cores and MacOS 15.2 SDK, HVF can virtualise FEAT_SME2. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr> Message-id: 20260306-sme2-hvf-v7-2-e72eeda41ed3@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Manos Pitsidianakis committed
Mar 6, 2026 at 14:45 UTC
55cd59813f148fd8adf00d8be8f36f623ec28ba9
1 file changed
+23
-13
target/arm/hvf/hvf.c
+23
-13
@@ -315,6 +315,7 @@ typedef struct ARMHostCPUFeatures {
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uint64_t features;
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uint64_t midr;
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uint32_t reset_sctlr;
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+ uint32_t sme_vq_supported;
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const char *dtb_compatible;
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} ARMHostCPUFeatures;
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@@ -1106,6 +1107,24 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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r |= hv_vcpu_config_get_feature_reg(config, regs[i].reg,
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&host_isar.idregs[regs[i].index]);
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}
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+
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+ if (__builtin_available(macOS 15.2, *)) {
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+ static const struct sme_isar_regs {
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+ hv_feature_reg_t reg;
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+ ARMIDRegisterIdx index;
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+ } sme_regs[] = {
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+ { HV_FEATURE_REG_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_IDX },
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+ { HV_FEATURE_REG_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_IDX },
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+ };
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+
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+ if (hvf_arm_sme2_supported()) {
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+ for (i = 0; i < ARRAY_SIZE(sme_regs); i++) {
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+ r |= hv_vcpu_config_get_feature_reg(config, sme_regs[i].reg,
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+ &host_isar.idregs[sme_regs[i].index]);
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+ }
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+ }
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+ }
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+
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os_release(config);
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/*
@@ -1121,19 +1140,6 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
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- /*
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- * Disable SME, which is not properly handled by QEMU hvf yet.
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- * To allow this through we would need to:
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- * - make sure that the SME state is correctly handled in the
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- * get_registers/put_registers functions
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- * - get the SME-specific CPU properties to work with accelerators
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- * other than TCG
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- * - fix any assumptions we made that SME implies SVE (since
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- * on the M4 there is SME but not SVE)
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- */
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- SET_IDREG(&host_isar, ID_AA64PFR1,
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- GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
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-
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ahcf->isar = host_isar;
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/*
@@ -1148,6 +1154,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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*/
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ahcf->reset_sctlr |= 0x00800000;
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+ ahcf->sme_vq_supported = hvf_arm_sme2_supported() ? hvf_arm_sme2_get_svl() : 0;
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+
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/* Make sure we don't advertise AArch32 support for EL0/EL1 */
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if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) != 0x11) {
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return false;
@@ -1199,6 +1207,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
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cpu->env.features = arm_host_cpu_features.features;
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cpu->midr = arm_host_cpu_features.midr;
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cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
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+ cpu->sme_vq.supported = arm_host_cpu_features.sme_vq_supported;
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}
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void hvf_arch_vcpu_destroy(CPUState *cpu)
@@ -1343,6 +1352,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
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arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);
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assert_hvf_ok(ret);
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+ aarch64_add_sme_properties(OBJECT(cpu));
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return 0;
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}
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