@samitouri / QOSamiQemu / commits / 564b0d05bc

target/arm: gate check on scr_el3 behind ARM_FEATURE_EL3 check

We shouldn't be reading SCR_EL3 unless ARM_FEATURE_EL3 is enabled, if it is then we check SCR_ECVEN allows tweaking the offset. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260624124527.1018912-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Alex Bennée committed Jun 24, 2026 at 13:45 UTC 564b0d05bc0fa7c60269fb159f797ce5a25357f6
1 file changed +4 -4
target/arm/helper.c
+4 -4
@@ -1413,10 +1413,10 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
1413
1414 static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
1415 {
1416 - if ((env->cp15.scr_el3 & SCR_ECVEN) &&
1417 - FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
1418 - arm_is_el2_enabled(env) &&
1419 - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
1416 + if ((!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_ECVEN))
1417 + && FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV)
1418 + && arm_is_el2_enabled(env)
1419 + && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
1420 return env->cp15.cntpoff_el2;
1421 }
1422 return 0;