target/arm: Implement Floating-point round to integral value (predicated, zeroing)
This is the various FRINT rounding modes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
56aef9cf6f22e08b4b203bfdc61ec542445421b1
2 files changed
+25
target/arm/tcg/sve.decode
+8
@@ -1240,6 +1240,14 @@ FRINTA_m 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
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FRINTX_m 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
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FRINTI_m 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
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+FRINTN_z 01100100 .. 011 000 100 ... ..... ..... @rd_pg_rn
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+FRINTP_z 01100100 .. 011 000 101 ... ..... ..... @rd_pg_rn
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+FRINTM_z 01100100 .. 011 000 110 ... ..... ..... @rd_pg_rn
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+FRINTZ_z 01100100 .. 011 000 111 ... ..... ..... @rd_pg_rn
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+FRINTA_z 01100100 .. 011 001 100 ... ..... ..... @rd_pg_rn
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+FRINTX_z 01100100 .. 011 001 110 ... ..... ..... @rd_pg_rn
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+FRINTI_z 01100100 .. 011 001 111 ... ..... ..... @rd_pg_rn
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+
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# SVE floating-point unary operations
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FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
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FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
target/arm/tcg/translate-sve.c
+17
@@ -4644,6 +4644,9 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
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TRANS_FEAT(FRINTI_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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frint_fns[a->esz], a, 0,
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a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
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+TRANS_FEAT(FRINTI_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ frint_fns[a->esz], a, 1,
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+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
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static gen_helper_gvec_3_ptr * const frintx_fns[] = {
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NULL,
@@ -4654,6 +4657,9 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = {
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TRANS_FEAT(FRINTX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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frintx_fns[a->esz], a, 0,
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a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
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+TRANS_FEAT(FRINTX_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ frintx_fns[a->esz], a, 1,
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+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
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static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
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ARMFPRounding mode, int data,
@@ -4694,6 +4700,17 @@ TRANS_FEAT(FRINTZ_m, aa64_sme_or_sve, do_frint_mode, a,
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TRANS_FEAT(FRINTA_m, aa64_sme_or_sve, do_frint_mode, a,
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FPROUNDING_TIEAWAY, 0, frint_fns[a->esz])
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+TRANS_FEAT(FRINTN_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_TIEEVEN, 1, frint_fns[a->esz])
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+TRANS_FEAT(FRINTP_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_POSINF, 1, frint_fns[a->esz])
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+TRANS_FEAT(FRINTM_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_NEGINF, 1, frint_fns[a->esz])
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+TRANS_FEAT(FRINTZ_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_ZERO, 1, frint_fns[a->esz])
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+TRANS_FEAT(FRINTA_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_TIEAWAY, 1, frint_fns[a->esz])
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+
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static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
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NULL, gen_helper_sve_frecpx_h,
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gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,