@samitouri / QOSamiQemu / commits / 56f98b2ec9

hw/misc/aspeed_sdmc: convert to use Resettable interface

Replace the legacy reset callback registered via device_class_set_legacy_reset() with the Resettable interface. Signed-off-by: Kane Chen <kane_chen@aspeedtech.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-8-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Kane Chen committed May 25, 2026 at 04:41 UTC 56f98b2ec9b751f14dc401005f26f27dd28b81d9
1 file changed +8 -6
hw/misc/aspeed_sdmc.c
+8 -6
@@ -199,9 +199,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
199 .valid.max_access_size = 4,
200 };
201
202 -static void aspeed_sdmc_reset(DeviceState *dev)
202 +static void aspeed_sdmc_reset_hold(Object *obj, ResetType type)
203 {
204 - AspeedSDMCState *s = ASPEED_SDMC(dev);
204 + AspeedSDMCState *s = ASPEED_SDMC(obj);
205 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
206
207 memset(s->regs, 0, sizeof(s->regs));
@@ -302,8 +302,9 @@ static const Property aspeed_sdmc_properties[] = {
302 static void aspeed_sdmc_class_init(ObjectClass *klass, const void *data)
303 {
304 DeviceClass *dc = DEVICE_CLASS(klass);
305 + ResettableClass *rc = RESETTABLE_CLASS(klass);
306 dc->realize = aspeed_sdmc_realize;
306 - device_class_set_legacy_reset(dc, aspeed_sdmc_reset);
307 + rc->phases.hold = aspeed_sdmc_reset_hold;
308 dc->desc = "ASPEED SDRAM Memory Controller";
309 dc->vmsd = &vmstate_aspeed_sdmc;
310 device_class_set_props(dc, aspeed_sdmc_properties);
@@ -560,9 +561,9 @@ static const TypeInfo aspeed_2600_sdmc_info = {
561 .class_init = aspeed_2600_sdmc_class_init,
562 };
563
563 -static void aspeed_2700_sdmc_reset(DeviceState *dev)
564 +static void aspeed_2700_sdmc_reset_hold(Object *obj, ResetType type)
565 {
565 - AspeedSDMCState *s = ASPEED_SDMC(dev);
566 + AspeedSDMCState *s = ASPEED_SDMC(obj);
567 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
568
569 memset(s->regs, 0, sizeof(s->regs));
@@ -676,10 +677,11 @@ static const uint64_t
677 static void aspeed_2700_sdmc_class_init(ObjectClass *klass, const void *data)
678 {
679 DeviceClass *dc = DEVICE_CLASS(klass);
680 + ResettableClass *rc = RESETTABLE_CLASS(klass);
681 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
682
683 dc->desc = "ASPEED 2700 SDRAM Memory Controller";
682 - device_class_set_legacy_reset(dc, aspeed_2700_sdmc_reset);
684 + rc->phases.hold = aspeed_2700_sdmc_reset_hold;
685
686 asc->is_bus64bit = true;
687 asc->max_ram_size = 8 * GiB;