target/ppc: Migrate atomic loads to decodetree
Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx, lqarx) to decodetree using the X-form layout. A shared helper (do_load_locked) is introduced for standard-width variants, while LQARX is handled separately due to its 128-bit semantics and register pairing constraints. The implementation preserves legacy behavior, including: - Reservation granularity and overwrite semantics - Alignment requirements - Invalid instruction cases for LQARX Testing: - Verified TCG equivalence with legacy implementation Signed-off-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-3-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Nikhil Kumar Singh committed
Aug 27, 2026 at 18:59 UTC
57432acb9cc84ac8b791bccdd60dc158de0be324
2 files changed
+63
-62
target/ppc/insn32.decode
+7
@@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
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##Extend Sign Word and Shift Left Immediate XS-form
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EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS
1311
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+## Load and Reserve Instructions
1313
+LBARX 011111 ..... ..... ..... 0000110100 . @X_rc
1314
+LHARX 011111 ..... ..... ..... 0001110100 . @X_rc
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+LWARX 011111 ..... ..... ..... 0000010100 . @X_rc
1316
+LDARX 011111 ..... ..... ..... 0001010100 . @X_rc
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+LQARX 011111 ..... ..... ..... 0100010100 . @X_rc
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+
1319
## Vector Division Instructions
1320
1321
VDIVSW 000100 ..... ..... ..... 00110001011 @VX
target/ppc/translate.c
+56
-62
@@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx)
2947
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
2948
}
2949
2950
-static void gen_load_locked(DisasContext *ctx, MemOp memop)
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-{
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- TCGv gpr = cpu_gpr[rD(ctx->opcode)];
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- TCGv t0 = tcg_temp_new();
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-
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- gen_set_access_type(ctx, ACCESS_RES);
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- gen_addr_reg_index(ctx, t0);
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- tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
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- tcg_gen_mov_tl(cpu_reserve, t0);
2959
- tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
2960
- tcg_gen_mov_tl(cpu_reserve_val, gpr);
2961
-}
2962
-
2963
-#define LARX(name, memop) \
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-static void gen_##name(DisasContext *ctx) \
2965
-{ \
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- gen_load_locked(ctx, memop); \
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-}
2968
-
2969
-/* lwarx */
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-LARX(lbarx, MO_UB)
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-LARX(lharx, MO_UW)
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-LARX(lwarx, MO_UL)
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-
2950
static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
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TCGv EA, TCGCond cond, int addend)
2952
{
@@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW)
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STCX(stwcx_, MO_UL)
3196
3197
#if defined(TARGET_PPC64)
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-/* ldarx */
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-LARX(ldarx, MO_UQ)
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/* stdcx. */
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STCX(stdcx_, MO_UQ)
3200
3227
-/* lqarx */
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-static void gen_lqarx(DisasContext *ctx)
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-{
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- int rd = rD(ctx->opcode);
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- TCGv EA, hi, lo;
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- TCGv_i128 t16;
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-
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- if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
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- (rd == rB(ctx->opcode)))) {
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- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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- return;
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- }
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-
3240
- gen_set_access_type(ctx, ACCESS_RES);
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- EA = tcg_temp_new();
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- gen_addr_reg_index(ctx, EA);
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-
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- /* Note that the low part is always in RD+1, even in LE mode. */
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- lo = cpu_gpr[rd + 1];
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- hi = cpu_gpr[rd];
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-
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- t16 = tcg_temp_new_i128();
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- tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN));
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- tcg_gen_extr_i128_i64(lo, hi, t16);
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-
3252
- tcg_gen_mov_tl(cpu_reserve, EA);
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- tcg_gen_movi_tl(cpu_reserve_length, 16);
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- tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val));
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- tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2));
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-}
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-
3201
/* stqcx. */
3202
static void gen_stqcx_(DisasContext *ctx)
3203
{
@@ -5741,6 +5684,62 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS *a)
5684
return true;
5685
}
5686
5687
+/*
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+ * Load-and-reserve core
5689
+ */
5690
+static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop)
5691
+{
5692
+ TCGv EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
5693
+ TCGv gpr = cpu_gpr[a->rt];
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+
5695
+ gen_set_access_type(ctx, ACCESS_RES);
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+
5697
+ tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN);
5698
+
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+ tcg_gen_mov_tl(cpu_reserve, EA);
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+ tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
5701
+
5702
+ tcg_gen_mov_tl(cpu_reserve_val, gpr);
5703
+
5704
+ return true;
5705
+}
5706
+
5707
+TRANS_FLAGS2(ATOMIC_ISA206, LBARX, do_load_locked, DEF_MEMOP(MO_UB))
5708
+TRANS_FLAGS2(ATOMIC_ISA206, LHARX, do_load_locked, DEF_MEMOP(MO_UW))
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+TRANS(LWARX, do_load_locked, DEF_MEMOP(MO_UL))
5710
+TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ))
5711
+
5712
+static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a)
5713
+{
5714
+ REQUIRE_64BIT(ctx);
5715
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
5716
+#if defined(TARGET_PPC64)
5717
+ TCGv EA;
5718
+ TCGv_i128 t16;
5719
+ /* Must use even register and avoid overlap */
5720
+ if (unlikely((a->rt & 1) || (a->rt == a->ra) || (a->rt == a->rb))) {
5721
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5722
+ return true;
5723
+ }
5724
+
5725
+ gen_set_access_type(ctx, ACCESS_RES);
5726
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
5727
+ t16 = tcg_temp_new_i128();
5728
+
5729
+ tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN));
5730
+ tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1], cpu_gpr[a->rt], t16);
5731
+ tcg_gen_mov_tl(cpu_reserve, EA);
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+ tcg_gen_movi_tl(cpu_reserve_length, 16);
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+ tcg_gen_st_i64(cpu_gpr[a->rt], tcg_env,
5734
+ offsetof(CPUPPCState, reserve_val));
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+ tcg_gen_st_i64(cpu_gpr[a->rt + 1], tcg_env,
5736
+ offsetof(CPUPPCState, reserve_val2));
5737
+#else
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+ qemu_build_not_reached();
5739
+#endif
5740
+ return true;
5741
+}
5742
+
5743
#include "translate/fixedpoint-impl.c.inc"
5744
5745
#include "translate/fp-impl.c.inc"
@@ -5853,9 +5852,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
5852
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
5853
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
5854
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
5856
-GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5857
-GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
5858
-GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
5855
GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
5856
GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
5857
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
@@ -5864,8 +5860,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
5860
#if defined(TARGET_PPC64)
5861
GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
5862
GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
5867
-GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
5868
-GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
5863
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
5864
GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
5865
#endif