hexagon: group cpu configurations in their own struct
This will be used in a follow up commit. Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/8f9a2e2ccfd2eeda73a63d1a6abbfd6e5458b44c.1776339451.git.matheus.bernardino@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Matheus Tavares Bernardino committed
Apr 16, 2026 at 04:38 UTC
5995de98c4699b3246f1dffa86b90f677b6e7684
4 files changed
+20
-17
target/hexagon/cpu.c
+7
-7
@@ -71,11 +71,11 @@ static const Property hexagon_cpu_properties[] = {
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TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *),
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DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0),
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#endif
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- DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
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- DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,
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- qdev_prop_uint32, target_ulong),
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- DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true),
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- DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, ieee_fp_extension, true),
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+ DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, cfg.lldb_compat, false),
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+ DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, cfg.lldb_stack_adjust,
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+ 0, qdev_prop_uint32, target_ulong),
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+ DEFINE_PROP_BOOL("short-circuit", HexagonCPU, cfg.short_circuit, true),
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+ DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, cfg.ieee_fp_extension, true),
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};
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const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
@@ -127,7 +127,7 @@ const char * const hexagon_gregnames[] = {
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static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
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{
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HexagonCPU *cpu = env_archcpu(env);
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- target_ulong stack_adjust = cpu->lldb_stack_adjust;
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+ target_ulong stack_adjust = cpu->cfg.lldb_stack_adjust;
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target_ulong stack_start = env->stack_start;
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target_ulong stack_size = 0x10000;
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@@ -239,7 +239,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
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{
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HexagonCPU *cpu = env_archcpu(env);
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- if (cpu->lldb_compat) {
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+ if (cpu->cfg.lldb_compat) {
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/*
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* When comparing with LLDB, it doesn't step through single-cycle
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* hardware loops the same way. So, we just skip them here
target/hexagon/cpu.h
+3
-7
@@ -186,15 +186,13 @@ typedef struct HexagonCPUClass {
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const HexagonCPUDef *hex_def;
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} HexagonCPUClass;
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+#include "cpu_bits.h"
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+
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struct ArchCPU {
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CPUState parent_obj;
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CPUHexagonState env;
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-
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- bool lldb_compat;
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- target_ulong lldb_stack_adjust;
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- bool short_circuit;
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- bool ieee_fp_extension;
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+ HexagonCPUConfig cfg;
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#ifndef CONFIG_USER_ONLY
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HexagonTLBState *tlb;
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uint32_t boot_addr;
@@ -204,8 +202,6 @@ struct ArchCPU {
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#endif
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};
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-#include "cpu_bits.h"
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-
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FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
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FIELD(TB_FLAGS, MMU_INDEX, 1, 3)
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FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)
target/hexagon/cpu_bits.h
+7
@@ -21,6 +21,13 @@
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#include "qemu/bitops.h"
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#include "cpu-qom.h"
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+typedef struct HexagonCPUConfig {
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+ bool lldb_compat;
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+ uint32_t lldb_stack_adjust;
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+ bool short_circuit;
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+ bool ieee_fp_extension;
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+} HexagonCPUConfig;
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+
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#define PCALIGN 4
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#define PCALIGN_MASK (PCALIGN - 1)
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target/hexagon/translate.c
+3
-3
@@ -1209,9 +1209,9 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
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ctx->num_hvx_insns = 0;
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ctx->branch_cond = TCG_COND_NEVER;
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ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);
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- ctx->short_circuit = hex_cpu->short_circuit;
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+ ctx->short_circuit = hex_cpu->cfg.short_circuit;
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ctx->hex_def = HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def;
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- ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;
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+ ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;
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#ifndef CONFIG_USER_ONLY
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ctx->num_cycles = 0;
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ctx->pcycle_enabled = FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED);
@@ -1268,7 +1268,7 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
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* so end the TLB after every packet.
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*/
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HexagonCPU *hex_cpu = env_archcpu(env);
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- if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
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+ if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
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ctx->base.is_jmp = DISAS_TOO_MANY;
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}
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}