target/arm: Separate syndrome functions for A32 and A64
Currently we have one syn_fp_access_trap() which we use for fp traps from A64 and from VFP and Neon A32. This means that A64 has to specify arguments that are always fixed for it (coproc and is_16bit) and A32 can't specify arguments it needs to (TA). Split it up into syn_a64_fp_access_trap() and syn_a32_fp_access_trap(). This is a refactor with no behavioural change. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260702184019.3431139-3-peter.maydell@linaro.org
Peter Maydell committed
Jul 2, 2026 at 19:40 UTC
59970c372c410d6d57d4b158f88e7bc56f170234
3 files changed
+24
-8
target/arm/syndrome.h
+22
-6
@@ -345,21 +345,37 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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/*
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* ISS encoding for an exception from an access to a register of
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- * instruction resulting from the FPEN or TFP traps.
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+ * instruction resulting from the FPEN or TFP traps. Note that
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+ * the TA and COPROC fields are only valid when an AArch32 insn
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+ * traps to AArch32 EL2; they are RES0 for traps to AArch64.
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*/
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-FIELD(FP_ISS, COPROC, 0, 4) /* ARMv7 only */
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+FIELD(FP_ISS, COPROC, 0, 4)
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+FIELD(FP_ISS, TA, 5, 1)
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FIELD(FP_ISS, COND, 20, 4)
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FIELD(FP_ISS, CV, 24, 1)
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-static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
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- int coproc)
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+static inline uint32_t syn_a64_fp_access_trap(int cv, int cond)
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{
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- /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
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+ /* AArch64 FP/SIMD trap: TA and coproc are RES0, insn is 64 bits */
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uint32_t res = syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP);
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- res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, FP_ISS, CV, cv);
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+ res = FIELD_DP32(res, FP_ISS, COND, cond);
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+
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+ return res;
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+}
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+
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+static inline uint32_t syn_a32_fp_access_trap(int cv, int cond,
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+ int ta, int coproc)
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+{
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+ /* AArch32 VFP or Neon trap: TA and coproc valid, insn is 64 bits */
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+ uint32_t res = syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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res = FIELD_DP32(res, FP_ISS, CV, cv);
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res = FIELD_DP32(res, FP_ISS, COND, cond);
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+ res = FIELD_DP32(res, FP_ISS, TA, ta);
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res = FIELD_DP32(res, FP_ISS, COPROC, coproc);
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return res;
target/arm/tcg/translate-a64.c
+1
-1
@@ -1439,7 +1439,7 @@ static bool fp_access_check_only(DisasContext *s)
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s->fp_access_checked = -1;
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gen_exception_insn_el(s, 0, EXCP_UDEF,
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- syn_fp_access_trap(1, 0xe, false, 0),
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+ syn_a64_fp_access_trap(1, 0xe),
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s->fp_excp_el);
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return false;
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}
target/arm/tcg/translate-vfp.c
+1
-1
@@ -228,7 +228,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
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* this field to 0xA.
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*/
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int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
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- uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
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+ uint32_t syn = syn_a32_fp_access_trap(1, 0xe, 0, coproc);
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gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el);
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return false;