hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP
The AST2700 SSP/TSP firmware accesses Privilege Controller MMIO regions that are not yet implemented in QEMU. This change adds unimplemented MMIO devices for the Privilege Controller blocks and maps them to their corresponding physical addresses in the SSP/TSP address space. These stub devices allow QEMU to safely handle firmware accesses and prevent spurious exceptions, while accurately reflecting the hardware memory map. No functional changes. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260706052701.1141740-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Jul 6, 2026 at 05:27 UTC
59a3b57bab6c1e7104b9ebaa70b3f1c85fc4f2e4
4 files changed
+27
hw/arm/aspeed_ast27x0-ssp.c
+12
@@ -22,10 +22,12 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
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[ASPEED_DEV_SDRAM] = 0x00000000,
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[ASPEED_DEV_SRAM0] = 0x70000000,
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[ASPEED_DEV_INTC] = 0x72100000,
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+ [ASPEED_DEV_PRIC0] = 0x72140000,
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[ASPEED_DEV_SCU] = 0x72C02000,
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[ASPEED_DEV_TIMER1] = 0x72C10000,
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[ASPEED_DEV_UART4] = 0x72C1A000,
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[ASPEED_DEV_IPC0] = 0x72C1C000,
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+ [ASPEED_DEV_PRIC1] = 0x74100000,
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[ASPEED_DEV_SCUIO] = 0x74C02000,
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[ASPEED_DEV_INTCIO] = 0x74C18000,
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[ASPEED_DEV_UART0] = 0x74C33000,
@@ -141,6 +143,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
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TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "scuio", &a->scuio,
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TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "pric0", &a->pric[0],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "pric1", &a->pric[1],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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}
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static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
@@ -255,6 +261,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
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"aspeed.scuio",
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sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
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+ "aspeed.pric0",
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+ sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
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+ "aspeed.pric1",
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+ sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
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}
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static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
hw/arm/aspeed_ast27x0-tsp.c
+12
@@ -22,10 +22,12 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
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[ASPEED_DEV_SDRAM] = 0x00000000,
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[ASPEED_DEV_SRAM0] = 0x70000000,
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[ASPEED_DEV_INTC] = 0x72100000,
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+ [ASPEED_DEV_PRIC0] = 0x72140000,
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[ASPEED_DEV_SCU] = 0x72C02000,
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[ASPEED_DEV_TIMER1] = 0x72C10000,
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[ASPEED_DEV_UART4] = 0x72C1A000,
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[ASPEED_DEV_IPC0] = 0x72C1C000,
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+ [ASPEED_DEV_PRIC1] = 0x74100000,
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[ASPEED_DEV_SCUIO] = 0x74C02000,
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[ASPEED_DEV_INTCIO] = 0x74C18000,
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[ASPEED_DEV_UART0] = 0x74C33000,
@@ -141,6 +143,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
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TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "scuio", &a->scuio,
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TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "pric0", &a->pric[0],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "pric1", &a->pric[1],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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}
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static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
@@ -255,6 +261,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
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"aspeed.scuio",
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sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
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+ "aspeed.pric0",
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+ sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
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+ "aspeed.pric1",
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+ sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
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}
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static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
include/hw/arm/aspeed_coprocessor.h
+1
@@ -48,6 +48,7 @@ struct Aspeed27x0CoprocessorState {
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AspeedINTCState intc[2];
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UnimplementedDeviceState ipc[2];
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UnimplementedDeviceState scuio;
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+ UnimplementedDeviceState pric[2];
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ARMv7MState armv7m;
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};
include/hw/arm/aspeed_soc.h
+2
@@ -295,6 +295,8 @@ enum {
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ASPEED_DEV_IOEXP1_INTCIO,
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ASPEED_DEV_IOEXP0_I3C,
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ASPEED_DEV_IOEXP1_I3C,
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+ ASPEED_DEV_PRIC0,
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+ ASPEED_DEV_PRIC1,
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};
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const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);