hw/riscv/riscv-iommu.c: make FCTL.BE read only 0
We do not support FCTL.BE equal to 1 hence do not allow this bit to be set by software. While we're at it: the riscv-iommu spec allows FCTL.GXL to be set freely and we do not have hardcoded restrictions on it, so make it writable. Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3576 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260625210833.3294437-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jun 25, 2026 at 18:08 UTC
5a3fd18f4f9b9c2a19c0800e88d7b38403e210ca
1 file changed
+3
-1
hw/riscv/riscv-iommu.c
+3
-1
@@ -2609,9 +2609,11 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
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/* Set power-on register state */
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stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap);
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+
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stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0);
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stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL],
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- ~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI));
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+ ~(RISCV_IOMMU_FCTL_GXL | RISCV_IOMMU_FCTL_WSI));
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+
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stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP],
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~(RISCV_IOMMU_DDTP_PPN | RISCV_IOMMU_DDTP_MODE));
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stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQB],