target/riscv: Fix size of pc, load_[val|res]
Fix to 64 bits in size and as these are mapped to TCG globals, be careful with host endianness when allocating globals. Casts are added to logging expressions to retain the correct size for TARGET_RISCV32. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-4-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
5aed8ac67e2dd49552178e9e4db7f8dd303c3d03
5 files changed
+17
-15
target/riscv/cpu.c
+1
-1
@@ -585,7 +585,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
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}
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#endif
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- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
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+ qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc);
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
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int csrno = i;
target/riscv/cpu.h
+3
-3
@@ -226,9 +226,9 @@ struct CPUArchState {
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uint8_t vxsat;
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bool vill;
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- target_ulong pc;
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- target_ulong load_res;
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- target_ulong load_val;
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+ uint64_t pc;
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+ uint64_t load_res;
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+ uint64_t load_val;
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/* Floating-Point state */
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uint64_t fpr[32]; /* assume both F and D extensions */
target/riscv/cpu_helper.c
+3
-3
@@ -2373,9 +2373,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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qemu_log_mask(CPU_LOG_INT,
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"%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", "
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- "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
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- __func__, env->mhartid, async, cause, env->pc, tval,
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- riscv_cpu_get_trap_name(cause, async));
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+ "epc:0x%"PRIx64", tval:0x"TARGET_FMT_lx", desc=%s\n",
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+ __func__, env->mhartid, async, cause, env->pc,
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+ tval, riscv_cpu_get_trap_name(cause, async));
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mode = env->priv <= PRV_S && cause < 64 &&
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(((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M;
target/riscv/machine.c
+3
-3
@@ -453,9 +453,9 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
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VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
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VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
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- VMSTATE_UINTTL(env.pc, RISCVCPU),
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- VMSTATE_UINTTL(env.load_res, RISCVCPU),
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- VMSTATE_UINTTL(env.load_val, RISCVCPU),
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+ VMSTATE_UINT64(env.pc, RISCVCPU),
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+ VMSTATE_UINT64(env.load_res, RISCVCPU),
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+ VMSTATE_UINT64(env.load_val, RISCVCPU),
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VMSTATE_UINTTL(env.frm, RISCVCPU),
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VMSTATE_UINTTL(env.badaddr, RISCVCPU),
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VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
target/riscv/translate.c
+7
-5
@@ -1484,6 +1484,10 @@ void riscv_translate_init(void)
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/* 32 bits in size, no offset needed */
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size_t vl_offset = offsetof(CPURISCVState, vl);
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size_t vstart_offset = offsetof(CPURISCVState, vstart);
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+ /* 64 bits in size mapped to TCGv, needs offset */
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+ size_t pc_offset = offsetof(CPURISCVState, pc) + field_offset;
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+ size_t res_offset = offsetof(CPURISCVState, load_res) + field_offset;
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+ size_t val_offset = offsetof(CPURISCVState, load_val) + field_offset;
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for (i = 1; i < 32; i++) {
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cpu_gpr[i] = tcg_global_mem_new(tcg_env,
@@ -1499,11 +1503,9 @@ void riscv_translate_init(void)
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offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
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}
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- cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
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+ cpu_pc = tcg_global_mem_new(tcg_env, pc_offset, "pc");
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cpu_vl = tcg_global_mem_new_i32(tcg_env, vl_offset, "vl");
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cpu_vstart = tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart");
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- load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
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- "load_res");
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- load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
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- "load_val");
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+ load_res = tcg_global_mem_new(tcg_env, res_offset, "load_res");
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+ load_val = tcg_global_mem_new(tcg_env, val_offset, "load_val");
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}