target/riscv: move custom_csrs logic to tcg-cpu.c
We have a couple of CPUs that has a set of custom CSRs that uses TCG specific APIs. Move the related code to tcg-cpu.c and do not set .custom_csrs if we're not in a TCG build. What we'll end up doing, sooner or later, is punting all these CPUs to tcg-cpu.c since they're all TCG specific and KVM has nothing to do with them. Another time. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703180538.3346781-12-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
5b9e32dd5cd4942e3bee9e8c494019e1d06987d2
3 files changed
+28
-21
target/riscv/cpu.c
+5
-21
@@ -544,19 +544,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
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}
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#endif
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-#ifndef CONFIG_USER_ONLY
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-static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
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-{
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- for (size_t i = 0; csr_list[i].csr_ops.name; i++) {
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- int csrno = csr_list[i].csrno;
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- const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops;
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- if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) {
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- riscv_set_csr_ops(csrno, csr_ops);
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- }
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- }
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-}
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-#endif
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-
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/* Used by csr.c and the KVM driver */
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target_ulong riscv_new_csr_seed(target_ulong new_value,
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target_ulong write_mask)
@@ -1268,11 +1255,6 @@ static void riscv_cpu_init(Object *obj)
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if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
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cpu->env.vext_ver = mcc->def->vext_spec;
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}
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-#ifndef CONFIG_USER_ONLY
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- if (mcc->def->custom_csrs) {
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- riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
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- }
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-#endif
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accel_cpu_instance_init(CPU(obj));
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}
@@ -2846,10 +2828,12 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data)
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riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg);
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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if (def->custom_csrs) {
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assert(!mcc->def->custom_csrs);
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mcc->def->custom_csrs = def->custom_csrs;
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}
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+#endif
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}
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if (!object_class_is_abstract(c)) {
@@ -3202,7 +3186,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.mvendorid = THEAD_VENDOR_ID,
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.cfg.max_satp_mode = VM_1_10_SV39,
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-#ifndef CONFIG_USER_ONLY
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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.custom_csrs = th_csr_list,
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#endif
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),
@@ -3248,7 +3232,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.marchid = 0x8d143000,
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.cfg.mvendorid = THEAD_VENDOR_ID,
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-#ifndef CONFIG_USER_ONLY
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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.custom_csrs = th_csr_list,
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#endif
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),
@@ -3454,7 +3438,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.ext_xmipscmov = true,
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.cfg.marchid = 0x8000000000000201,
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.cfg.mvendorid = MIPS_VENDOR_ID,
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-#ifndef CONFIG_USER_ONLY
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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.custom_csrs = mips_csr_list,
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#endif
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),
target/riscv/cpu.h
+2
@@ -591,7 +591,9 @@ typedef struct RISCVCPUDef {
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int32_t vext_spec;
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RISCVCPUConfig cfg;
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bool bare;
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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const RISCVCSR *custom_csrs;
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+#endif
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/* This is just a setter for env->num_triggers. */
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uint32_t num_triggers;
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} RISCVCPUDef;
target/riscv/tcg/tcg-cpu.c
+21
@@ -38,6 +38,7 @@
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#include "system/tcg.h"
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#include "exec/icount.h"
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#include "target/riscv/tcg/debug.h"
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+#include "target/riscv/tcg/csr.h"
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#endif
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/* Hash that stores user set extensions */
@@ -1650,10 +1651,30 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
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}
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+#ifndef CONFIG_USER_ONLY
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+static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
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+{
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+ for (size_t i = 0; csr_list[i].csr_ops.name; i++) {
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+ int csrno = csr_list[i].csrno;
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+ const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops;
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+ if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) {
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+ riscv_set_csr_ops(csrno, csr_ops);
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+ }
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+ }
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+}
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+#endif
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+
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static void riscv_tcg_cpu_instance_init(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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Object *obj = OBJECT(cpu);
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+#ifndef CONFIG_USER_ONLY
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+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
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+
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+ if (mcc->def->custom_csrs) {
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+ riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
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+ }
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+#endif
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misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
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multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);