target/arm: Add FGWTE3_EL3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260806172709.333300-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 6, 2026 at 10:27 UTC
5dd83f42eb6f05f8986cd4fc0d69b3732d3fa47f
4 files changed
+27
-1
target/arm/cpregs.h
+1
@@ -385,6 +385,7 @@ typedef enum CPAccessResult {
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/* Indexes into fgt_write[] */
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#define FGTREG_HFGWTR 0
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#define FGTREG_HDFGWTR 1
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+#define FGTREG_FGWTE3 2
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/* Indexes into fgt_exec[] */
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#define FGTREG_HFGITR 0
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target/arm/cpu-features.h
+5
@@ -1467,6 +1467,11 @@ static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0;
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}
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+static inline bool isar_feature_aa64_fgwte3(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64MMFR4, FGWTE3) != 0;
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+}
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+
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/*
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* Note the E2H0 ID fields is signed, increasingly negative as more
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* isn't implemented.
target/arm/cpu.h
+1
-1
@@ -553,7 +553,7 @@ typedef struct CPUArchState {
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* FEAT_FGT2 will add more elements to these arrays.
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*/
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uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
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- uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
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+ uint64_t fgt_write[3]; /* HFGWTR, HDFGWTR, FGWTE3 */
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uint64_t fgt_exec[1]; /* HFGITR */
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/* RME registers */
target/arm/helper.c
+20
@@ -6394,6 +6394,22 @@ static const ARMCPRegInfo fpmr_reginfo[] = {
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}
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};
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+static void fgwte3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ /* All bits are W1S and can only be cleared by cpu reset. */
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+ env->cp15.fgt_write[FGTREG_FGWTE3] |= value;
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+}
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+
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+static const ARMCPRegInfo fgwte3_reginfo[] = {
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+ { .name = "FGWTE3_EL3", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 5,
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+ .access = PL3_RW, .resetvalue = 0,
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+ .writefn = fgwte3_write, .raw_writefn = raw_write,
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+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_FGWTE3])
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+ },
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+};
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+
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void register_cp_regs_for_features(ARMCPU *cpu)
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{
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/* Register all the coprocessor registers based on feature bits */
@@ -7705,6 +7721,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, ccsidr2_reginfo);
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}
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+ if (cpu_isar_feature(aa64_fgwte3, cpu)) {
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+ define_arm_cp_regs(cpu, fgwte3_reginfo);
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+ }
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+
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define_pm_cpregs(cpu);
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define_gcs_cpregs(cpu);
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}