hw/arm/aspeed: Introduce AST1040 A0 SoC model
The AST1040 is based on an ARM Cortex-M4F CPU core. Since QEMU currently does not provide Cortex-M4F support, use the existing Cortex-M4 CPU model as a temporary replacement. This initial implementation provides the basic infrastructure required to boot firmware and run a minimal firmware shell, including: - ARM Cortex-M4 CPU integration - NVIC interrupt controller support - Internal HyperRAM and SRAM memory regions - SCU integration - UART devices and interrupt wiring AST1040 SCU behavior is compatible with the AST2700 SCUIO model, so reuse the existing AST2700 SCUIO implementation directly instead of introducing another identical SCU model. This reduces duplicate code and helps minimize long-term codebase maintenance. Several peripherals are currently modeled as unimplemented devices and can be added incrementally in future updates. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
May 25, 2026 at 05:30 UTC
5f249abc9bab265237ab15c162960e6dafe89800
2 files changed
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hw/arm/aspeed_ast1040.c
new
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@@ -0,0 +1,254 @@
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+/*
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+ * ASPEED AST1040 SoC
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+ *
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+ * Copyright (C) 2026 ASPEED Technology Inc.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qapi/error.h"
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+#include "system/address-spaces.h"
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+#include "system/system.h"
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+#include "hw/core/qdev-clock.h"
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+#include "hw/misc/unimp.h"
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+#include "hw/arm/aspeed_soc.h"
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+
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+static const hwaddr aspeed_soc_ast1040_memmap[] = {
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+ [ASPEED_DEV_SRAM1] = 0x00000000, /* Hyper RAM */
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+ [ASPEED_DEV_FMC] = 0x74000000,
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+ [ASPEED_DEV_SPI0] = 0x74010000,
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+ [ASPEED_DEV_SPI1] = 0x74020000,
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+ [ASPEED_DEV_PWM] = 0x740C0000,
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+ [ASPEED_DEV_UDC] = 0x74120000,
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+ [ASPEED_DEV_SRAM0] = 0x74B80000,
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+ [ASPEED_DEV_ADC] = 0x74C00000,
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+ [ASPEED_DEV_JTAG0] = 0x74C01000,
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+ [ASPEED_DEV_SCU] = 0x74C02000,
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+ [ASPEED_DEV_ESPI] = 0x74C05000,
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+ [ASPEED_DEV_JTAG1] = 0x74C09000,
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+ [ASPEED_DEV_GPIO] = 0x74C0B000,
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+ [ASPEED_DEV_SGPIOM0] = 0x74C0C000,
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+ [ASPEED_DEV_SGPIOM1] = 0x74C0D000,
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+ [ASPEED_DEV_I2C] = 0x74C0F000,
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+ [ASPEED_DEV_I3C] = 0x74C20000,
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+ [ASPEED_DEV_UART0] = 0x74C33000,
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+ [ASPEED_DEV_UART1] = 0x74C33100,
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+ [ASPEED_DEV_UART2] = 0x74C33200,
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+ [ASPEED_DEV_UART3] = 0x74C33300,
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+ [ASPEED_DEV_UART4] = 0x74C33400,
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+ [ASPEED_DEV_UART5] = 0x74C33500,
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+ [ASPEED_DEV_UART6] = 0x74C33600,
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+ [ASPEED_DEV_UART7] = 0x74C33700,
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+ [ASPEED_DEV_UART8] = 0x74C33800,
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+ [ASPEED_DEV_UART9] = 0x74C33900,
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+ [ASPEED_DEV_UART10] = 0x74C33A00,
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+ [ASPEED_DEV_UART11] = 0x74C33B00,
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+ [ASPEED_DEV_UART12] = 0x74C33C00,
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+ [ASPEED_DEV_WDT] = 0x74C37000,
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+ [ASPEED_DEV_TIMER1] = 0x74C3A000,
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+};
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+
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+static const int aspeed_soc_ast1040_irqmap[] = {
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+ [ASPEED_DEV_ESPI] = 10,
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+ [ASPEED_DEV_I2C] = 64, /* 64 ~ 77 */
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+ [ASPEED_DEV_ADC] = 80,
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+ [ASPEED_DEV_GPIO] = 82,
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+ [ASPEED_DEV_SGPIOM0] = 85,
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+ [ASPEED_DEV_TIMER1] = 92,
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+ [ASPEED_DEV_I3C] = 96, /* 96 ~ 103 */
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+ [ASPEED_DEV_WDT] = 112,
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+ [ASPEED_DEV_FMC] = 121,
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+ [ASPEED_DEV_SPI0] = 122,
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+ [ASPEED_DEV_SPI1] = 123,
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+ [ASPEED_DEV_PWM] = 125,
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+ [ASPEED_DEV_UART0] = 135,
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+ [ASPEED_DEV_UART1] = 136,
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+ [ASPEED_DEV_UART2] = 137,
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+ [ASPEED_DEV_UART3] = 138,
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+ [ASPEED_DEV_UART4] = 139,
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+ [ASPEED_DEV_UART5] = 140,
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+ [ASPEED_DEV_UART6] = 141,
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+ [ASPEED_DEV_UART7] = 142,
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+ [ASPEED_DEV_UART8] = 143,
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+ [ASPEED_DEV_UART9] = 144,
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+ [ASPEED_DEV_UART10] = 145,
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+ [ASPEED_DEV_UART11] = 146,
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+ [ASPEED_DEV_UART12] = 147,
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+ [ASPEED_DEV_JTAG0] = 162,
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+};
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+
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+static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)
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+{
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+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
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+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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+
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+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
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+}
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+
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+static void aspeed_soc_ast1040_init(Object *obj)
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+{
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+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
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+ AspeedSoCState *s = ASPEED_SOC(obj);
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+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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+ int i;
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+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
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+
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+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
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+
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+ /* AST1040 uses the AST2700 SCUIO model */
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+ object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCUIO);
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+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
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+
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+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
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+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
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+
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+ for (i = 0; i < sc->uarts_num; i++) {
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+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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+ }
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+
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+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "sgpiom[0]", &s->sgpiom[0],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "sgpiom[1]", &s->sgpiom[1],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "jtag[0]", &s->jtag[0],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+ object_initialize_child(obj, "jtag[1]", &s->jtag[1],
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+ TYPE_UNIMPLEMENTED_DEVICE);
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+}
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+
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+static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
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+{
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+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
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+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
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+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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+ g_autofree char *hyperram_name = NULL;
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+ g_autofree char *sram_name = NULL;
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+ DeviceState *armv7m;
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+ Error *err = NULL;
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+ int uart;
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+ int i;
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+
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+ if (!clock_has_source(s->sysclk)) {
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+ error_setg(errp, "sysclk clock must be wired up by the board code");
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+ return;
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+ }
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+
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+ /* AST1040 CPU Core */
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+ armv7m = DEVICE(&a->armv7m);
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+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
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+ qdev_prop_set_string(armv7m, "cpu-type",
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+ aspeed_soc_cpu_type(sc->valid_cpu_types));
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+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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+ object_property_set_link(OBJECT(&a->armv7m), "memory",
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+ OBJECT(s->memory), &error_abort);
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+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
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+
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+ /* Internal SRAM */
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+ sram_name = g_strdup_printf("aspeed.sram.%d",
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+ CPU(a->armv7m.cpu)->cpu_index);
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+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
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+ sc->sram_size[0], &err);
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+ if (err) {
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+ error_propagate(errp, err);
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+ return;
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+ }
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+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
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+ &s->sram[0]);
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+
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+ /* Internal Hyper RAM */
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+ hyperram_name = g_strdup_printf("aspeed.hyperram.%d",
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+ CPU(a->armv7m.cpu)->cpu_index);
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+ memory_region_init_ram(&s->sram[1], OBJECT(s), hyperram_name,
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+ sc->sram_size[1], &err);
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+ if (err) {
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+ error_propagate(errp, err);
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+ return;
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+ }
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+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
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+ &s->sram[1]);
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+
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+ /* SCU */
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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+ return;
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+ }
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+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
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+ sc->memmap[ASPEED_DEV_SCU]);
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+
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+ /* UART */
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+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
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+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
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+ sc->memmap[uart], errp)) {
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+ return;
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+ }
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
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+ aspeed_soc_ast1040_get_irq(s, uart));
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+ }
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+
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+ /* Unimplemented peripherals */
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
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+ "aspeed.pwm",
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+ sc->memmap[ASPEED_DEV_PWM], 0x10000);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),
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+ "aspeed.espi",
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+ sc->memmap[ASPEED_DEV_ESPI], 0x1000);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),
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+ "aspeed.udc",
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+ sc->memmap[ASPEED_DEV_UDC], 0x4000);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[0]),
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+ "aspeed.sgpiom0",
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+ sc->memmap[ASPEED_DEV_SGPIOM0], 0x1000);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[1]),
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+ "aspeed.sgpiom1",
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+ sc->memmap[ASPEED_DEV_SGPIOM1], 0x1000);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
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+ "aspeed.jtag0",
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+ sc->memmap[ASPEED_DEV_JTAG0], 0x100);
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+
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+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
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+ "aspeed.jtag1",
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+ sc->memmap[ASPEED_DEV_JTAG1], 0x100);
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+}
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+
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+static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
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+{
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+ static const char * const valid_cpu_types[] = {
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+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
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+ NULL
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+ };
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
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+
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+ /* Reason: The Aspeed SoC can only be instantiated from a board */
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+ dc->user_creatable = false;
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+ dc->realize = aspeed_soc_ast1040_realize;
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+
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+ sc->valid_cpu_types = valid_cpu_types;
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+ sc->silicon_rev = AST1040_A0_SILICON_REV;
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+ sc->sram_size[0] = 128 * KiB;
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+ sc->sram_size[1] = 16 * MiB; /* Hyper RAM */
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+ sc->uarts_num = 13;
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+ sc->uarts_base = ASPEED_DEV_UART0;
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+ sc->irqmap = aspeed_soc_ast1040_irqmap;
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+ sc->memmap = aspeed_soc_ast1040_memmap;
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+ sc->num_cpus = 1;
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+}
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+
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+static const TypeInfo aspeed_soc_ast1040_types[] = {
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+ {
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+ .name = "ast1040-a0",
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+ .parent = TYPE_ASPEED10X0_SOC,
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+ .instance_init = aspeed_soc_ast1040_init,
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+ .class_init = aspeed_soc_ast1040_class_init,
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+ }
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+};
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+
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+DEFINE_TYPES(aspeed_soc_ast1040_types)
hw/arm/meson.build
+2
-1
@@ -63,7 +63,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
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'aspeed_ast2600_gb200nvl.c',
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'aspeed_ast2600_rainier.c',
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'aspeed_ast10x0.c',
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- 'aspeed_ast10x0_evb.c'))
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+ 'aspeed_ast10x0_evb.c',
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+ 'aspeed_ast1040.c'))
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arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
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'aspeed_ast1700.c',
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'aspeed_ast27x0.c',