hw/hexagon/virt: connect pl011 UART interrupt
Wire pl011's sysbus IRQ into l2vic at IRQ 15. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260806042723.3785369-13-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 5, 2026 at 21:27 UTC
5f8e903c02404a8c880b4bfcfbe1589d0a36e911
1 file changed
+8
-2
hw/hexagon/virt.c
+8
-2
@@ -39,6 +39,7 @@ enum {
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* VIRTIO_IRQ_BASE + VIRTIO_DEV_COUNT - 1
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*/
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static const int VIRTIO_IRQ_BASE = 16;
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+static const int VIRT_UART0_IRQ = 15;
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static const MemMapEntry base_memmap[] = {
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[VIRT_UART0] = { 0x10000000, 0x00000200 },
@@ -143,7 +144,7 @@ static int32_t fdt_add_clocks(const HexagonVirtMachineState *vms)
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}
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static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart,
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- int32_t clk_phandle)
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+ int32_t clk_phandle, int32_t l2vic_phandle)
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{
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char *nodename;
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hwaddr base = base_memmap[uart].base;
@@ -161,6 +162,8 @@ static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart,
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qdev_connect_clock_in(dev, "clk", vms->apb_clk);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, base);
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+ sysbus_connect_irq(s, 0,
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+ qdev_get_gpio_in(vms->parent_obj.l2vic, VIRT_UART0_IRQ));
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nodename = g_strdup_printf("/pl011@%" PRIx64, base);
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qemu_fdt_add_subnode(ms->fdt, nodename);
@@ -168,6 +171,9 @@ static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart,
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/* Note that we can't use setprop_string because of the embedded NUL */
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qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size);
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+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", VIRT_UART0_IRQ);
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+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
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+ l2vic_phandle);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", clk_phandle,
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clk_phandle);
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qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames,
@@ -342,7 +348,7 @@ static void virt_init(MachineState *ms)
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fdt_add_cpu_nodes(vms);
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clk_phandle = fdt_add_clocks(vms);
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- fdt_add_uart(vms, VIRT_UART0, clk_phandle);
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+ fdt_add_uart(vms, VIRT_UART0, clk_phandle, l2vic_phandle);
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hexagon_load_fdt(vms);
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}