@samitouri / QOSamiQemu / commits / 5ff65fac2d

hw/dma/omap_dma: Remove support for dma_3_0 and dma_3_2

The omap_dma device has support for modelling different variants of the DMA block, as enumerated by the omap_dma_model enum: 3_0, 3_1 and 3_2. However, our one remaining OMAP SoC always passes omap_dma_3_1 into the omap_dma_init() function, so the handling for 3_0 and 3_2 is never used. Remove the support for the other versions; this lets us delete entirely two large functions that were specific to 3.2 DMA to the LCD controller, and all their associated fields in the omap_dma_lcd_channel_s struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260512203414.3633237-8-peter.maydell@linaro.org

Peter Maydell committed May 12, 2026 at 21:34 UTC 5ff65fac2d883ec846e7628090f89f35a2e21ff5

2 files changed +15 -361

hw/dma/omap_dma.c

+15 -333

@@ -110,7 +110,6 @@ struct omap_dma_s {

110 omap_clk clk;

111 qemu_irq irq[4];

112 void (*intr_update)(struct omap_dma_s *s);

113 - enum omap_dma_model model;

113 int omap_3_1_mapping_disabled;

114

115 uint32_t gcr;

@@ -752,10 +751,7 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s,

751 break;

752

753 case 0x02: /* SYS_DMA_CCR_CH0 */

755 - if (s->model <= omap_dma_3_1)

756 - *value = 0 << 10; /* FIFO_FLUSH reads as 0 */

757 - else

758 - *value = ch->omap_3_1_compatible_disable << 10;

754 + *value = 0 << 10; /* FIFO_FLUSH reads as 0 */

755 *value |= (ch->mode[1] << 14) |

756 (ch->mode[0] << 12) |

757 (ch->end_prog << 11) |

@@ -892,8 +888,6 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,

888 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);

889 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);

890 ch->end_prog = (value & 0x0800) >> 11;

895 - if (s->model >= omap_dma_3_2)

896 - ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;

891 ch->repeat = (value & 0x0200) >> 9;

892 ch->auto_init = (value & 0x0100) >> 8;

893 ch->priority = (value & 0x0040) >> 6;

@@ -1002,250 +996,6 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,

996 return 0;

997 }

998

1005 -static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,

1006 - uint16_t value)

1007 -{

1008 - switch (offset) {

1009 - case 0xbc0: /* DMA_LCD_CSDP */

1010 - s->brust_f2 = (value >> 14) & 0x3;

1011 - s->pack_f2 = (value >> 13) & 0x1;

1012 - s->data_type_f2 = (1 << ((value >> 11) & 0x3));

1013 - s->brust_f1 = (value >> 7) & 0x3;

1014 - s->pack_f1 = (value >> 6) & 0x1;

1015 - s->data_type_f1 = (1 << ((value >> 0) & 0x3));

1016 - break;

1017 -

1018 - case 0xbc2: /* DMA_LCD_CCR */

1019 - s->mode_f2 = (value >> 14) & 0x3;

1020 - s->mode_f1 = (value >> 12) & 0x3;

1021 - s->end_prog = (value >> 11) & 0x1;

1022 - s->omap_3_1_compatible_disable = (value >> 10) & 0x1;

1023 - s->repeat = (value >> 9) & 0x1;

1024 - s->auto_init = (value >> 8) & 0x1;

1025 - s->running = (value >> 7) & 0x1;

1026 - s->priority = (value >> 6) & 0x1;

1027 - s->bs = (value >> 4) & 0x1;

1028 - break;

1029 -

1030 - case 0xbc4: /* DMA_LCD_CTRL */

1031 - s->dst = (value >> 8) & 0x1;

1032 - s->src = ((value >> 6) & 0x3) << 1;

1033 - s->condition = 0;

1034 - /* Assume no bus errors and thus no BUS_ERROR irq bits. */

1035 - s->interrupts = (value >> 1) & 1;

1036 - s->dual = value & 1;

1037 - break;

1038 -

1039 - case 0xbc8: /* TOP_B1_L */

1040 - s->src_f1_top &= 0xffff0000;

1041 - s->src_f1_top |= 0x0000ffff & value;

1042 - break;

1043 -

1044 - case 0xbca: /* TOP_B1_U */

1045 - s->src_f1_top &= 0x0000ffff;

1046 - s->src_f1_top |= (uint32_t)value << 16;

1047 - break;

1048 -

1049 - case 0xbcc: /* BOT_B1_L */

1050 - s->src_f1_bottom &= 0xffff0000;

1051 - s->src_f1_bottom |= 0x0000ffff & value;

1052 - break;

1053 -

1054 - case 0xbce: /* BOT_B1_U */

1055 - s->src_f1_bottom &= 0x0000ffff;

1056 - s->src_f1_bottom |= (uint32_t) value << 16;

1057 - break;

1058 -

1059 - case 0xbd0: /* TOP_B2_L */

1060 - s->src_f2_top &= 0xffff0000;

1061 - s->src_f2_top |= 0x0000ffff & value;

1062 - break;

1063 -

1064 - case 0xbd2: /* TOP_B2_U */

1065 - s->src_f2_top &= 0x0000ffff;

1066 - s->src_f2_top |= (uint32_t) value << 16;

1067 - break;

1068 -

1069 - case 0xbd4: /* BOT_B2_L */

1070 - s->src_f2_bottom &= 0xffff0000;

1071 - s->src_f2_bottom |= 0x0000ffff & value;

1072 - break;

1073 -

1074 - case 0xbd6: /* BOT_B2_U */

1075 - s->src_f2_bottom &= 0x0000ffff;

1076 - s->src_f2_bottom |= (uint32_t) value << 16;

1077 - break;

1078 -

1079 - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */

1080 - s->element_index_f1 = value;

1081 - break;

1082 -

1083 - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */

1084 - s->frame_index_f1 &= 0xffff0000;

1085 - s->frame_index_f1 |= 0x0000ffff & value;

1086 - break;

1087 -

1088 - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */

1089 - s->frame_index_f1 &= 0x0000ffff;

1090 - s->frame_index_f1 |= (uint32_t) value << 16;

1091 - break;

1092 -

1093 - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */

1094 - s->element_index_f2 = value;

1095 - break;

1096 -

1097 - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */

1098 - s->frame_index_f2 &= 0xffff0000;

1099 - s->frame_index_f2 |= 0x0000ffff & value;

1100 - break;

1101 -

1102 - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */

1103 - s->frame_index_f2 &= 0x0000ffff;

1104 - s->frame_index_f2 |= (uint32_t) value << 16;

1105 - break;

1106 -

1107 - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */

1108 - s->elements_f1 = value;

1109 - break;

1110 -

1111 - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */

1112 - s->frames_f1 = value;

1113 - break;

1114 -

1115 - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */

1116 - s->elements_f2 = value;

1117 - break;

1118 -

1119 - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */

1120 - s->frames_f2 = value;

1121 - break;

1122 -

1123 - case 0xbea: /* DMA_LCD_LCH_CTRL */

1124 - s->lch_type = value & 0xf;

1125 - break;

1126 -

1127 - default:

1128 - return 1;

1129 - }

1130 - return 0;

1131 -}

1132 -

1133 -static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,

1134 - uint16_t *ret)

1135 -{

1136 - switch (offset) {

1137 - case 0xbc0: /* DMA_LCD_CSDP */

1138 - *ret = (s->brust_f2 << 14) |

1139 - (s->pack_f2 << 13) |

1140 - ((s->data_type_f2 >> 1) << 11) |

1141 - (s->brust_f1 << 7) |

1142 - (s->pack_f1 << 6) |

1143 - ((s->data_type_f1 >> 1) << 0);

1144 - break;

1145 -

1146 - case 0xbc2: /* DMA_LCD_CCR */

1147 - *ret = (s->mode_f2 << 14) |

1148 - (s->mode_f1 << 12) |

1149 - (s->end_prog << 11) |

1150 - (s->omap_3_1_compatible_disable << 10) |

1151 - (s->repeat << 9) |

1152 - (s->auto_init << 8) |

1153 - (s->running << 7) |

1154 - (s->priority << 6) |

1155 - (s->bs << 4);

1156 - break;

1157 -

1158 - case 0xbc4: /* DMA_LCD_CTRL */

1159 - qemu_irq_lower(s->irq);

1160 - *ret = (s->dst << 8) |

1161 - ((s->src & 0x6) << 5) |

1162 - (s->condition << 3) |

1163 - (s->interrupts << 1) |

1164 - s->dual;

1165 - break;

1166 -

1167 - case 0xbc8: /* TOP_B1_L */

1168 - *ret = s->src_f1_top & 0xffff;

1169 - break;

1170 -

1171 - case 0xbca: /* TOP_B1_U */

1172 - *ret = s->src_f1_top >> 16;

1173 - break;

1174 -

1175 - case 0xbcc: /* BOT_B1_L */

1176 - *ret = s->src_f1_bottom & 0xffff;

1177 - break;

1178 -

1179 - case 0xbce: /* BOT_B1_U */

1180 - *ret = s->src_f1_bottom >> 16;

1181 - break;

1182 -

1183 - case 0xbd0: /* TOP_B2_L */

1184 - *ret = s->src_f2_top & 0xffff;

1185 - break;

1186 -

1187 - case 0xbd2: /* TOP_B2_U */

1188 - *ret = s->src_f2_top >> 16;

1189 - break;

1190 -

1191 - case 0xbd4: /* BOT_B2_L */

1192 - *ret = s->src_f2_bottom & 0xffff;

1193 - break;

1194 -

1195 - case 0xbd6: /* BOT_B2_U */

1196 - *ret = s->src_f2_bottom >> 16;

1197 - break;

1198 -

1199 - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */

1200 - *ret = s->element_index_f1;

1201 - break;

1202 -

1203 - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */

1204 - *ret = s->frame_index_f1 & 0xffff;

1205 - break;

1206 -

1207 - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */

1208 - *ret = s->frame_index_f1 >> 16;

1209 - break;

1210 -

1211 - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */

1212 - *ret = s->element_index_f2;

1213 - break;

1214 -

1215 - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */

1216 - *ret = s->frame_index_f2 & 0xffff;

1217 - break;

1218 -

1219 - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */

1220 - *ret = s->frame_index_f2 >> 16;

1221 - break;

1222 -

1223 - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */

1224 - *ret = s->elements_f1;

1225 - break;

1226 -

1227 - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */

1228 - *ret = s->frames_f1;

1229 - break;

1230 -

1231 - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */

1232 - *ret = s->elements_f2;

1233 - break;

1234 -

1235 - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */

1236 - *ret = s->frames_f2;

1237 - break;

1238 -

1239 - case 0xbea: /* DMA_LCD_LCH_CTRL */

1240 - *ret = s->lch_type;

1241 - break;

1242 -

1243 - default:

1244 - return 1;

1245 - }

1246 - return 0;

1247 -}

1248 -

999 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,

1000 uint16_t value)

1001 {

@@ -1462,12 +1212,10 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)

1212

1213 switch (addr) {

1214 case 0x300 ... 0x3fe:

1465 - if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {

1466 - if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))

1467 - break;

1468 - return ret;

1215 + if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) {

1216 + break;

1217 }

1470 - /* Fall through. */

1218 + return ret;

1219 case 0x000 ... 0x2fe:

1220 reg = addr & 0x3f;

1221 ch = (addr >> 6) & 0x0f;

@@ -1476,20 +1224,13 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)

1224 return ret;

1225

1226 case 0x404 ... 0x4fe:

1479 - if (s->model <= omap_dma_3_1)

1480 - break;

1481 - /* Fall through. */

1227 + break;

1228 case 0x400:

1229 if (omap_dma_sys_read(s, addr, &ret))

1230 break;

1231 return ret;

1232

1233 case 0xb00 ... 0xbfe:

1488 - if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {

1489 - if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))

1490 - break;

1491 - return ret;

1492 - }

1234 break;

1235 }

1236

@@ -1511,12 +1252,10 @@ static void omap_dma_write(void *opaque, hwaddr addr,

1252

1253 switch (addr) {

1254 case 0x300 ... 0x3fe:

1514 - if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {

1515 - if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))

1516 - break;

1517 - return;

1255 + if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) {

1256 + break;

1257 }

1519 - /* Fall through. */

1258 + return;

1259 case 0x000 ... 0x2fe:

1260 reg = addr & 0x3f;

1261 ch = (addr >> 6) & 0x0f;

@@ -1525,20 +1264,13 @@ static void omap_dma_write(void *opaque, hwaddr addr,

1264 return;

1265

1266 case 0x404 ... 0x4fe:

1528 - if (s->model <= omap_dma_3_1)

1529 - break;

1530 - /* fall through */

1267 + break;

1268 case 0x400:

1269 if (omap_dma_sys_write(s, addr, value))

1270 break;

1271 return;

1272

1273 case 0xb00 ... 0xbfe:

1537 - if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {

1538 - if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))

1539 - break;

1540 - return;

1541 - }

1274 break;

1275 }

1276

@@ -1577,51 +1309,6 @@ static void omap_dma_clk_update(void *opaque, int line, int on)

1309 soc_dma_set_request(s->ch[i].dma, on);

1310 }

1311

1580 -static void omap_dma_setcaps(struct omap_dma_s *s)

1581 -{

1582 - switch (s->model) {

1583 - default:

1584 - case omap_dma_3_1:

1585 - break;

1586 - case omap_dma_3_2:

1587 - /* XXX Only available for sDMA */

1588 - s->caps[0] =

1589 - (1 << 19) | /* Constant Fill Capability */

1590 - (1 << 18); /* Transparent BLT Capability */

1591 - s->caps[1] =

1592 - (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */

1593 - s->caps[2] =

1594 - (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */

1595 - (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */

1596 - (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */

1597 - (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */

1598 - (1 << 4) | /* DST_CONST_ADRS_CPBLTY */

1599 - (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */

1600 - (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */

1601 - (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */

1602 - (1 << 0); /* SRC_CONST_ADRS_CPBLTY */

1603 - s->caps[3] =

1604 - (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */

1605 - (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */

1606 - (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */

1607 - (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */

1608 - (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */

1609 - (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */

1610 - (1 << 1) | /* FRAME_SYNCHR_CPBLTY */

1611 - (1 << 0); /* ELMNT_SYNCHR_CPBLTY */

1612 - s->caps[4] =

1613 - (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */

1614 - (1 << 6) | /* SYNC_STATUS_CPBLTY */

1615 - (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */

1616 - (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */

1617 - (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */

1618 - (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */

1619 - (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */

1620 - (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */

1621 - break;

1622 - }

1623 -}

1624 -

1312 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,

1313 MemoryRegion *sysmem,

1314 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,

@@ -1630,20 +1317,16 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,

1317 int num_irqs, memsize, i;

1318 struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);

1319

1633 - if (model <= omap_dma_3_1) {

1634 - num_irqs = 6;

1635 - memsize = 0x800;

1636 - } else {

1637 - num_irqs = 16;

1638 - memsize = 0xc00;

1639 - }

1640 - s->model = model;

1320 + assert(model == omap_dma_3_1);

1321 +

1322 + num_irqs = 6;

1323 + memsize = 0x800;

1324 s->mpu = mpu;

1325 s->clk = clk;

1326 s->lcd_ch.irq = lcd_irq;

1327 s->lcd_ch.mpu = mpu;

1328

1646 - s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);

1329 + s->dma = soc_dma_init(9);

1330 s->dma->freq = omap_clk_getrate(clk);

1331 s->dma->transfer_fn = omap_dma_transfer_generic;

1332 s->dma->setup_fn = omap_dma_transfer_setup;

@@ -1656,12 +1339,11 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,

1339 s->ch[i].sibling = &s->ch[i + 6];

1340 s->ch[i + 6].sibling = &s->ch[i];

1341 }

1659 - for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {

1342 + for (i = 8; i >= 0; i--) {

1343 s->ch[i].dma = &s->dma->ch[i];

1344 s->dma->ch[i].opaque = &s->ch[i];

1345 }

1346

1664 - omap_dma_setcaps(s);

1347 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));

1348 omap_dma_reset(s->dma);

1349 omap_dma_clk_update(s, 0, 1);

include/hw/arm/omap.h

-28

@@ -216,34 +216,6 @@ struct omap_dma_lcd_channel_s {

216 hwaddr src_f2_top;

217 hwaddr src_f2_bottom;

218

219 - /* Used in OMAP DMA 3.2 gigacell */

220 - unsigned char brust_f1;

221 - unsigned char pack_f1;

222 - unsigned char data_type_f1;

223 - unsigned char brust_f2;

224 - unsigned char pack_f2;

225 - unsigned char data_type_f2;

226 - unsigned char end_prog;

227 - unsigned char repeat;

228 - unsigned char auto_init;

229 - unsigned char priority;

230 - unsigned char fs;

231 - unsigned char running;

232 - unsigned char bs;

233 - unsigned char omap_3_1_compatible_disable;

234 - unsigned char dst;

235 - unsigned char lch_type;

236 - int16_t element_index_f1;

237 - int16_t element_index_f2;

238 - int32_t frame_index_f1;

239 - int32_t frame_index_f2;

240 - uint16_t elements_f1;

241 - uint16_t frames_f1;

242 - uint16_t elements_f2;

243 - uint16_t frames_f2;

244 - omap_dma_addressing_t mode_f1;

245 - omap_dma_addressing_t mode_f2;

246 -

219 /* Destination port is fixed. */

220 int interrupts;

221 int condition;