target/ppc: Move VMX integer arithmetic and BCD instructions to decodetree.
Move below instructions to decodetree specification : vadd{u, s}{b, h, w, d}m[.], vsub{u, s}{b, h, w, d}m[.], vmuluwm[.], vmul10{u, eu, ecu, cu}q[.] : VX-form bcd{add, sub}[.], bcd{s, us}[.], bcdcpsgn[.], bcdct{sq, n}[.], bcdcf{sq, z, n}[.], bcdctz[.], bcdsetsgn[.], bcdsr[.], bcd{u,}trunc[.] : VX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-25-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Shivang Upadhyay committed
Aug 27, 2026 at 18:59 UTC
6021ec75195d1ef06f9c2fb26739ea48908e5437
5 files changed
+199
-223
target/ppc/helper.h
+15
-15
@@ -349,21 +349,21 @@ DEF_HELPER_FLAGS_3(vshasigmaw, TCG_CALL_NO_RWG, void, avr, avr, i32)
349
DEF_HELPER_FLAGS_3(vshasigmad, TCG_CALL_NO_RWG, void, avr, avr, i32)
350
DEF_HELPER_FLAGS_4(vpermxor, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
351
352
-DEF_HELPER_FLAGS_4(bcdadd, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
353
-DEF_HELPER_FLAGS_4(bcdsub, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
354
-DEF_HELPER_FLAGS_3(bcdcfn, TCG_CALL_NO_RWG, i32, avr, avr, i32)
355
-DEF_HELPER_FLAGS_3(bcdctn, TCG_CALL_NO_RWG, i32, avr, avr, i32)
356
-DEF_HELPER_FLAGS_3(bcdcfz, TCG_CALL_NO_RWG, i32, avr, avr, i32)
357
-DEF_HELPER_FLAGS_3(bcdctz, TCG_CALL_NO_RWG, i32, avr, avr, i32)
358
-DEF_HELPER_FLAGS_3(bcdcfsq, TCG_CALL_NO_RWG, i32, avr, avr, i32)
359
-DEF_HELPER_FLAGS_3(bcdctsq, TCG_CALL_NO_RWG, i32, avr, avr, i32)
360
-DEF_HELPER_FLAGS_4(bcdcpsgn, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
361
-DEF_HELPER_FLAGS_3(bcdsetsgn, TCG_CALL_NO_RWG, i32, avr, avr, i32)
362
-DEF_HELPER_FLAGS_4(bcds, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
363
-DEF_HELPER_FLAGS_4(bcdus, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
364
-DEF_HELPER_FLAGS_4(bcdsr, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
365
-DEF_HELPER_FLAGS_4(bcdtrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
366
-DEF_HELPER_FLAGS_4(bcdutrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
352
+DEF_HELPER_FLAGS_4(BCDADD, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
353
+DEF_HELPER_FLAGS_4(BCDSUB, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
354
+DEF_HELPER_FLAGS_3(BCDCFN, TCG_CALL_NO_RWG, i32, avr, avr, i32)
355
+DEF_HELPER_FLAGS_3(BCDCTN, TCG_CALL_NO_RWG, i32, avr, avr, i32)
356
+DEF_HELPER_FLAGS_3(BCDCFZ, TCG_CALL_NO_RWG, i32, avr, avr, i32)
357
+DEF_HELPER_FLAGS_3(BCDCTZ, TCG_CALL_NO_RWG, i32, avr, avr, i32)
358
+DEF_HELPER_FLAGS_3(BCDCFSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32)
359
+DEF_HELPER_FLAGS_3(BCDCTSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32)
360
+DEF_HELPER_FLAGS_4(BCDCPSGN, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
361
+DEF_HELPER_FLAGS_3(BCDSETSGN, TCG_CALL_NO_RWG, i32, avr, avr, i32)
362
+DEF_HELPER_FLAGS_4(BCDS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
363
+DEF_HELPER_FLAGS_4(BCDUS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
364
+DEF_HELPER_FLAGS_4(BCDSR, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
365
+DEF_HELPER_FLAGS_4(BCDTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
366
+DEF_HELPER_FLAGS_4(BCDUTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32)
367
368
DEF_HELPER_4(XSADDDP, void, env, vsr, vsr, vsr)
369
DEF_HELPER_5(xsaddqp, void, env, i32, vsr, vsr, vsr)
target/ppc/insn32.decode
+39
@@ -90,6 +90,9 @@
90
&VX vrt vra vrb
91
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
92
93
+&VX_ps vrt vra vrb ps
94
+@VX_ps ...... vrt:5 vra:5 vrb:5 . ps:1 ........ . &VX_ps
95
+
96
&VX_bf bf vra vrb
97
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
98
@@ -108,6 +111,9 @@
111
&VX_tb vrt vrb
112
@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
113
114
+&VX_tb_ps vrt vrb ps
115
+@VX_tb_ps ...... vrt:5 ..... vrb:5 . ps:1 ......... &VX_tb_ps
116
+
117
&X rt ra rb
118
@X ...... rt:5 ra:5 rb:5 .......... . &X
119
@@ -991,6 +997,10 @@ VADDSBS 000100 ..... ..... ..... 01100000000 @VX
997
VADDSHS 000100 ..... ..... ..... 01101000000 @VX
998
VADDSWS 000100 ..... ..... ..... 01110000000 @VX
999
1000
+VADDUBM 000100 ..... ..... ..... 00000000000 @VX
1001
+VADDUHM 000100 ..... ..... ..... 00001000000 @VX
1002
+VADDUWM 000100 ..... ..... ..... 00010000000 @VX
1003
+VADDUDM 000100 ..... ..... ..... 00011000000 @VX
1004
VADDUBS 000100 ..... ..... ..... 01000000000 @VX
1005
VADDUHS 000100 ..... ..... ..... 01001000000 @VX
1006
VADDUWS 000100 ..... ..... ..... 01010000000 @VX
@@ -1006,6 +1016,10 @@ VSUBSBS 000100 ..... ..... ..... 11100000000 @VX
1016
VSUBSHS 000100 ..... ..... ..... 11101000000 @VX
1017
VSUBSWS 000100 ..... ..... ..... 11110000000 @VX
1018
1019
+VSUBUBM 000100 ..... ..... ..... 10000000000 @VX
1020
+VSUBUHM 000100 ..... ..... ..... 10001000000 @VX
1021
+VSUBUWM 000100 ..... ..... ..... 10010000000 @VX
1022
+VSUBUDM 000100 ..... ..... ..... 10011000000 @VX
1023
VSUBUBS 000100 ..... ..... ..... 11000000000 @VX
1024
VSUBUHS 000100 ..... ..... ..... 11001000000 @VX
1025
VSUBUWS 000100 ..... ..... ..... 11010000000 @VX
@@ -1099,6 +1113,13 @@ VMULHSD 000100 ..... ..... ..... 01111001001 @VX
1113
VMULHUD 000100 ..... ..... ..... 01011001001 @VX
1114
VMULLD 000100 ..... ..... ..... 00111001001 @VX
1115
1116
+VMULUWM 000100 ..... ..... ..... 00010001001 @VX
1117
+
1118
+VMUL10UQ 000100 ..... ..... ..... 01000000001 @VX
1119
+VMUL10EUQ 000100 ..... ..... ..... 01001000001 @VX
1120
+VMUL10ECUQ 000100 ..... ..... ..... 00001000001 @VX
1121
+VMUL10CUQ 000100 ..... ..... ..... 00000000001 @VX
1122
+
1123
## Vector Multiply-Sum Instructions
1124
1125
VMSUMUBM 000100 ..... ..... ..... ..... 100100 @VA
@@ -1141,6 +1162,24 @@ VPKSWSS 000100 ..... ..... ..... 0011100111 0 @VX
1162
VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX
1163
VPKPX 000100 ..... ..... ..... 0110000111 0 @VX
1164
1165
+## Decimal Integer Arithmetic Instructions
1166
+
1167
+BCDADD 000100 ..... ..... ..... 1.000000001 @VX_ps
1168
+BCDSUB 000100 ..... ..... ..... 1.001000001 @VX_ps
1169
+BCDUS 000100 ..... ..... ..... 10010000001 @VX
1170
+BCDS 000100 ..... ..... ..... 1.011000001 @VX_ps
1171
+BCDCTSQ 000100 ..... 00000 ..... 10110000001 @VX_tb
1172
+BCDCTN 000100 ..... 00101 ..... 10110000001 @VX_tb
1173
+BCDCFSQ 000100 ..... 00010 ..... 1.110000001 @VX_tb_ps
1174
+BCDCTZ 000100 ..... 00100 ..... 1.110000001 @VX_tb_ps
1175
+BCDCFZ 000100 ..... 00110 ..... 1.110000001 @VX_tb_ps
1176
+BCDCFN 000100 ..... 00111 ..... 1.110000001 @VX_tb_ps
1177
+BCDSETSGN 000100 ..... 11111 ..... 1.110000001 @VX_tb_ps
1178
+BCDCPSGN 000100 ..... ..... ..... 01101000001 @VX
1179
+BCDSR 000100 ..... ..... ..... 1.111000001 @VX_ps
1180
+BCDTRUNC 000100 ..... ..... ..... 1.100000001 @VX_ps
1181
+BCDUTRUNC 000100 ..... ..... ..... 10101000001 @VX
1182
+
1183
# VSX Load/Store Instructions
1184
1185
LXSD 111001 ..... ..... .............. 10 @DS
target/ppc/int_helper.c
+16
-16
@@ -2348,7 +2348,7 @@ static void bcd_sub_mag(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, int *invalid,
2348
*overflow = carry;
2349
}
2350
2351
-uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2351
+uint32_t helper_BCDADD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2352
{
2353
2354
int sgna = bcd_get_sgn(a);
@@ -2395,7 +2395,7 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2395
return cr;
2396
}
2397
2398
-uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2398
+uint32_t helper_BCDSUB(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2399
{
2400
ppc_avr_t bcopy = *b;
2401
int sgnb = bcd_get_sgn(b);
@@ -2406,10 +2406,10 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2406
}
2407
/* else invalid ... defer to bcdadd code for proper handling */
2408
2409
- return helper_bcdadd(r, a, &bcopy, ps);
2409
+ return helper_BCDADD(r, a, &bcopy, ps);
2410
}
2411
2412
-uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2412
+uint32_t helper_BCDCFN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2413
{
2414
int i;
2415
int cr = 0;
@@ -2445,7 +2445,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2445
return cr;
2446
}
2447
2448
-uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2448
+uint32_t helper_BCDCTN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2449
{
2450
int i;
2451
int cr = 0;
@@ -2479,7 +2479,7 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2479
return cr;
2480
}
2481
2482
-uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2482
+uint32_t helper_BCDCFZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2483
{
2484
int i;
2485
int cr = 0;
@@ -2523,7 +2523,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2523
return cr;
2524
}
2525
2526
-uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2526
+uint32_t helper_BCDCTZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2527
{
2528
int i;
2529
int cr = 0;
@@ -2582,7 +2582,7 @@ static inline int ucmp128(uint64_t alo, uint64_t ahi,
2582
(ahi > bhi ? 1 : -1);
2583
}
2584
2585
-uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2585
+uint32_t helper_BCDCFSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2586
{
2587
int i;
2588
int cr;
@@ -2640,7 +2640,7 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2640
return cr;
2641
}
2642
2643
-uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2643
+uint32_t helper_BCDCTSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2644
{
2645
uint8_t i;
2646
int cr;
@@ -2680,7 +2680,7 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2680
return cr;
2681
}
2682
2683
-uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2683
+uint32_t helper_BCDCPSGN(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2684
{
2685
int i;
2686
int invalid = 0;
@@ -2703,7 +2703,7 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2703
return bcd_cmp_zero(r);
2704
}
2705
2706
-uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2706
+uint32_t helper_BCDSETSGN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2707
{
2708
int sgnb = bcd_get_sgn(b);
2709
@@ -2717,7 +2717,7 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
2717
return bcd_cmp_zero(r);
2718
}
2719
2720
-uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2720
+uint32_t helper_BCDS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2721
{
2722
int cr;
2723
int i = a->VsrSB(7);
@@ -2753,7 +2753,7 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2753
return cr;
2754
}
2755
2756
-uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2756
+uint32_t helper_BCDUS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2757
{
2758
int cr;
2759
int i;
@@ -2790,7 +2790,7 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2790
return cr;
2791
}
2792
2793
-uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2793
+uint32_t helper_BCDSR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2794
{
2795
int cr;
2796
int unused = 0;
@@ -2836,7 +2836,7 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2836
return cr;
2837
}
2838
2839
-uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2839
+uint32_t helper_BCDTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2840
{
2841
uint64_t mask;
2842
uint32_t ox_flag = 0;
@@ -2869,7 +2869,7 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2869
return bcd_cmp_zero(&ret) | ox_flag;
2870
}
2871
2872
-uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2872
+uint32_t helper_BCDUTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
2873
{
2874
int i;
2875
uint64_t mask;
target/ppc/translate/vmx-impl.c.inc
+129
-170
@@ -142,7 +142,8 @@ static void gen_mtvscr(DisasContext *ctx)
142
gen_helper_mtvscr(tcg_env, val);
143
}
144
145
-static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
145
+static bool do_vx_vmul10(DisasContext *ctx, arg_VX *a,
146
+ bool add_cin, bool ret_carry)
147
{
148
TCGv_i64 t0;
149
TCGv_i64 t1;
@@ -150,10 +151,7 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
151
TCGv_i64 avr;
152
TCGv_i64 ten, z;
153
153
- if (unlikely(!ctx->altivec_enabled)) {
154
- gen_exception(ctx, POWERPC_EXCP_VPU);
155
- return;
156
- }
154
+ REQUIRE_VECTOR(ctx);
155
156
t0 = tcg_temp_new_i64();
157
t1 = tcg_temp_new_i64();
@@ -163,54 +161,32 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
161
z = tcg_constant_i64(0);
162
163
if (add_cin) {
166
- get_avr64(avr, rA(ctx->opcode), false);
164
+ get_avr64(avr, a->vra, false);
165
tcg_gen_mulu2_i64(t0, t1, avr, ten);
168
- get_avr64(avr, rB(ctx->opcode), false);
166
+ get_avr64(avr, a->vrb, false);
167
tcg_gen_andi_i64(t2, avr, 0xF);
168
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z);
171
- set_avr64(rD(ctx->opcode), avr, false);
169
+ set_avr64(a->vrt, avr, false);
170
} else {
173
- get_avr64(avr, rA(ctx->opcode), false);
171
+ get_avr64(avr, a->vra, false);
172
tcg_gen_mulu2_i64(avr, t2, avr, ten);
175
- set_avr64(rD(ctx->opcode), avr, false);
173
+ set_avr64(a->vrt, avr, false);
174
}
175
176
if (ret_carry) {
179
- get_avr64(avr, rA(ctx->opcode), true);
177
+ get_avr64(avr, a->vra, true);
178
tcg_gen_mulu2_i64(t0, t1, avr, ten);
179
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z);
182
- set_avr64(rD(ctx->opcode), avr, false);
183
- set_avr64(rD(ctx->opcode), z, true);
180
+ set_avr64(a->vrt, avr, false);
181
+ set_avr64(a->vrt, z, true);
182
} else {
185
- get_avr64(avr, rA(ctx->opcode), true);
183
+ get_avr64(avr, a->vra, true);
184
tcg_gen_mul_i64(t0, avr, ten);
185
tcg_gen_add_i64(avr, t0, t2);
188
- set_avr64(rD(ctx->opcode), avr, true);
186
+ set_avr64(a->vrt, avr, true);
187
}
190
-}
191
-
192
-#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
193
- static void glue(gen_, name)(DisasContext *ctx) \
194
- { gen_vx_vmul10(ctx, add_cin, ret_carry); }
195
-
196
-GEN_VX_VMUL10(vmul10uq, 0, 0);
197
-GEN_VX_VMUL10(vmul10euq, 1, 0);
198
-GEN_VX_VMUL10(vmul10cuq, 0, 1);
199
-GEN_VX_VMUL10(vmul10ecuq, 1, 1);
188
201
-#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
202
-static void glue(gen_, name)(DisasContext *ctx) \
203
-{ \
204
- if (unlikely(!ctx->altivec_enabled)) { \
205
- gen_exception(ctx, POWERPC_EXCP_VPU); \
206
- return; \
207
- } \
208
- \
209
- tcg_op(vece, \
210
- avr_full_offset(rD(ctx->opcode)), \
211
- avr_full_offset(rA(ctx->opcode)), \
212
- avr_full_offset(rB(ctx->opcode)), \
213
- 16, 16); \
189
+ return true;
190
}
191
192
#define GEN_VXFORM(name, opc2, opc3) \
@@ -338,19 +314,6 @@ static void glue(gen_, name)(DisasContext *ctx) \
314
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
315
}
316
341
-GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
342
-GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
343
- vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
344
-GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
345
-GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
346
- vmul10ecuq, PPC_NONE, PPC2_ISA300)
347
-GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
348
-GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
349
-GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
350
-GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
351
-GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
352
-GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
353
-
317
static bool do_vmrg(DisasContext *ctx, arg_VX *a,
318
void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
319
{
@@ -370,6 +333,38 @@ TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB);
333
TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH);
334
TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW);
335
336
+static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece,
337
+ void (*gen_op)(unsigned, uint32_t, uint32_t,
338
+ uint32_t, uint32_t, uint32_t))
339
+{
340
+ REQUIRE_VECTOR(ctx);
341
+
342
+ gen_op(vece,
343
+ avr_full_offset(a->vrt),
344
+ avr_full_offset(a->vra),
345
+ avr_full_offset(a->vrb),
346
+ 16, 16);
347
+
348
+ return true;
349
+}
350
+
351
+TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add)
352
+TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add)
353
+TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add)
354
+TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add)
355
+
356
+TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub)
357
+TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub)
358
+TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub)
359
+TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub)
360
+
361
+TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul)
362
+
363
+TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true)
364
+TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true)
365
+TRANS_FLAGS2(ISA300, VMUL10UQ, do_vx_vmul10, false, false)
366
+TRANS_FLAGS2(ISA300, VMUL10EUQ, do_vx_vmul10, true, false)
367
+
368
static void trans_vmrgew(DisasContext *ctx)
369
{
370
int VT = rD(ctx->opcode);
@@ -684,7 +679,6 @@ static void trans_vclzd(DisasContext *ctx)
679
set_avr64(VT, avr, false);
680
}
681
687
-GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
682
GEN_VXFORM(vsrv, 2, 28);
683
GEN_VXFORM(vslv, 2, 29);
684
GEN_VXFORM(vslo, 6, 16);
@@ -2523,126 +2517,93 @@ GEN_VXFORM(vpmsumb, 4, 16)
2517
GEN_VXFORM(vpmsumh, 4, 17)
2518
GEN_VXFORM(vpmsumw, 4, 18)
2519
2526
-#define GEN_BCD(op) \
2527
-static void gen_##op(DisasContext *ctx) \
2528
-{ \
2529
- TCGv_ptr ra, rb, rd; \
2530
- TCGv_i32 ps; \
2531
- \
2532
- if (unlikely(!ctx->altivec_enabled)) { \
2533
- gen_exception(ctx, POWERPC_EXCP_VPU); \
2534
- return; \
2535
- } \
2536
- \
2537
- ra = gen_avr_ptr(rA(ctx->opcode)); \
2538
- rb = gen_avr_ptr(rB(ctx->opcode)); \
2539
- rd = gen_avr_ptr(rD(ctx->opcode)); \
2540
- \
2541
- ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
2542
- \
2543
- gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
2544
-}
2545
-
2546
-#define GEN_BCD2(op) \
2547
-static void gen_##op(DisasContext *ctx) \
2548
-{ \
2549
- TCGv_ptr rd, rb; \
2550
- TCGv_i32 ps; \
2551
- \
2552
- if (unlikely(!ctx->altivec_enabled)) { \
2553
- gen_exception(ctx, POWERPC_EXCP_VPU); \
2554
- return; \
2555
- } \
2556
- \
2557
- rb = gen_avr_ptr(rB(ctx->opcode)); \
2558
- rd = gen_avr_ptr(rD(ctx->opcode)); \
2559
- \
2560
- ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
2561
- \
2562
- gen_helper_##op(cpu_crf[6], rd, rb, ps); \
2563
-}
2564
-
2565
-GEN_BCD(bcdadd)
2566
-GEN_BCD(bcdsub)
2567
-GEN_BCD2(bcdcfn)
2568
-GEN_BCD2(bcdctn)
2569
-GEN_BCD2(bcdcfz)
2570
-GEN_BCD2(bcdctz)
2571
-GEN_BCD2(bcdcfsq)
2572
-GEN_BCD2(bcdctsq)
2573
-GEN_BCD2(bcdsetsgn)
2574
-GEN_BCD(bcdcpsgn);
2575
-GEN_BCD(bcds);
2576
-GEN_BCD(bcdus);
2577
-GEN_BCD(bcdsr);
2578
-GEN_BCD(bcdtrunc);
2579
-GEN_BCD(bcdutrunc);
2580
-
2581
-static void gen_xpnd04_1(DisasContext *ctx)
2582
-{
2583
- switch (opc4(ctx->opcode)) {
2584
- case 0:
2585
- gen_bcdctsq(ctx);
2586
- break;
2587
- case 2:
2588
- gen_bcdcfsq(ctx);
2589
- break;
2590
- case 4:
2591
- gen_bcdctz(ctx);
2592
- break;
2593
- case 5:
2594
- gen_bcdctn(ctx);
2595
- break;
2596
- case 6:
2597
- gen_bcdcfz(ctx);
2598
- break;
2599
- case 7:
2600
- gen_bcdcfn(ctx);
2601
- break;
2602
- case 31:
2603
- gen_bcdsetsgn(ctx);
2604
- break;
2605
- default:
2606
- gen_invalid(ctx);
2607
- break;
2608
- }
2520
+static bool do_bcd_ps(DisasContext *ctx, arg_VX_ps *a,
2521
+ void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr,
2522
+ TCGv_ptr, TCGv_i32))
2523
+{
2524
+ TCGv_ptr ra, rb, rd;
2525
+ TCGv_i32 ps;
2526
+
2527
+ REQUIRE_VECTOR(ctx);
2528
+
2529
+ ra = gen_avr_ptr(a->vra);
2530
+ rb = gen_avr_ptr(a->vrb);
2531
+ rd = gen_avr_ptr(a->vrt);
2532
+ ps = tcg_constant_i32(a->ps);
2533
+
2534
+ helper(cpu_crf[6], rd, ra, rb, ps);
2535
+ return true;
2536
}
2537
2611
-static void gen_xpnd04_2(DisasContext *ctx)
2612
-{
2613
- switch (opc4(ctx->opcode)) {
2614
- case 0:
2615
- gen_bcdctsq(ctx);
2616
- break;
2617
- case 2:
2618
- gen_bcdcfsq(ctx);
2619
- break;
2620
- case 4:
2621
- gen_bcdctz(ctx);
2622
- break;
2623
- case 6:
2624
- gen_bcdcfz(ctx);
2625
- break;
2626
- case 7:
2627
- gen_bcdcfn(ctx);
2628
- break;
2629
- case 31:
2630
- gen_bcdsetsgn(ctx);
2631
- break;
2632
- default:
2633
- gen_invalid(ctx);
2634
- break;
2635
- }
2538
+static bool do_bcd(DisasContext *ctx, arg_VX *a,
2539
+ void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr,
2540
+ TCGv_ptr, TCGv_i32))
2541
+{
2542
+ TCGv_ptr ra, rb, rd;
2543
+ TCGv_i32 ps;
2544
+
2545
+ REQUIRE_VECTOR(ctx);
2546
+
2547
+ ra = gen_avr_ptr(a->vra);
2548
+ rb = gen_avr_ptr(a->vrb);
2549
+ rd = gen_avr_ptr(a->vrt);
2550
+ ps = tcg_constant_i32(0);
2551
+
2552
+ helper(cpu_crf[6], rd, ra, rb, ps);
2553
+ return true;
2554
}
2555
2638
-GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2639
- bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2640
-GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2641
- bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2642
-GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2643
- bcds, PPC_NONE, PPC2_ISA300)
2644
-GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2645
- bcdus, PPC_NONE, PPC2_ISA300)
2556
+static bool do_bcd_tb(DisasContext *ctx, arg_VX_tb *a,
2557
+ void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32))
2558
+{
2559
+ TCGv_ptr rd, rb;
2560
+ TCGv_i32 ps;
2561
+
2562
+ REQUIRE_VECTOR(ctx);
2563
+
2564
+ rb = gen_avr_ptr(a->vrb);
2565
+ rd = gen_avr_ptr(a->vrt);
2566
+
2567
+ ps = tcg_constant_i32(0);
2568
+
2569
+ helper(cpu_crf[6], rd, rb, ps);
2570
+
2571
+ return true;
2572
+}
2573
+
2574
+static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a,
2575
+ void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32))
2576
+{
2577
+ TCGv_ptr rd, rb;
2578
+ TCGv_i32 ps;
2579
+
2580
+ REQUIRE_VECTOR(ctx);
2581
+
2582
+ rb = gen_avr_ptr(a->vrb);
2583
+ rd = gen_avr_ptr(a->vrt);
2584
+
2585
+ ps = tcg_constant_i32(a->ps);
2586
+
2587
+ helper(cpu_crf[6], rd, rb, ps);
2588
+
2589
+ return true;
2590
+}
2591
+
2592
+TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD)
2593
+TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB)
2594
+TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS)
2595
+TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS)
2596
+TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN)
2597
+TRANS_FLAGS2(ISA300, BCDCTN, do_bcd_tb, gen_helper_BCDCTN)
2598
+TRANS_FLAGS2(ISA300, BCDCFZ, do_bcd_tb_ps, gen_helper_BCDCFZ)
2599
+TRANS_FLAGS2(ISA300, BCDCTZ, do_bcd_tb_ps, gen_helper_BCDCTZ)
2600
+TRANS_FLAGS2(ISA300, BCDCFSQ, do_bcd_tb_ps, gen_helper_BCDCFSQ)
2601
+TRANS_FLAGS2(ISA300, BCDCTSQ, do_bcd_tb, gen_helper_BCDCTSQ)
2602
+TRANS_FLAGS2(ISA300, BCDSETSGN, do_bcd_tb_ps, gen_helper_BCDSETSGN)
2603
+TRANS_FLAGS2(ISA300, BCDCPSGN, do_bcd, gen_helper_BCDCPSGN)
2604
+TRANS_FLAGS2(ISA300, BCDTRUNC, do_bcd_ps, gen_helper_BCDTRUNC)
2605
+TRANS_FLAGS2(ISA300, BCDUTRUNC, do_bcd, gen_helper_BCDUTRUNC)
2606
+TRANS_FLAGS2(ISA300, BCDSR, do_bcd_ps, gen_helper_BCDSR)
2607
2608
static void gen_vsbox(DisasContext *ctx)
2609
{
@@ -3502,5 +3463,3 @@ TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper_VMODUQ)
3463
#undef GEN_VXFORM_NOA
3464
#undef GEN_VXFORM_UIMM
3465
#undef GEN_VAFORM_PAIRED
3505
-
3506
-#undef GEN_BCD2
target/ppc/translate/vmx-ops.c.inc
-22
@@ -24,39 +24,17 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
24
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
25
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
26
27
-GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
28
-GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE),
29
-GEN_VXFORM(vadduwm, 0, 2),
30
-GEN_VXFORM_207(vaddudm, 0, 3),
31
-GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
32
-GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
33
-GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
34
-GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
35
-GEN_VXFORM_300(bcds, 0, 27),
27
GEN_VXFORM_300(vextublx, 6, 24),
28
GEN_VXFORM_300(vextuhlx, 6, 25),
29
GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
30
GEN_VXFORM_300(vextubrx, 6, 28),
31
GEN_VXFORM_300(vextuhrx, 6, 29),
32
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
42
-GEN_VXFORM_207(vmuluwm, 4, 2),
33
GEN_VXFORM_300(vsrv, 2, 28),
34
GEN_VXFORM_300(vslv, 2, 29),
35
GEN_VXFORM(vslo, 6, 16),
36
GEN_VXFORM(vsro, 6, 17),
37
48
-GEN_VXFORM(xpnd04_1, 0, 22),
49
-GEN_VXFORM_300(bcdsr, 0, 23),
50
-GEN_VXFORM_300(bcdsr, 0, 31),
51
-GEN_VXFORM_300_EXT(vmul10uq, 0, 8, 0x0000F800),
52
-GEN_VXFORM_300(vmul10euq, 0, 9),
53
-GEN_VXFORM_300(bcdcpsgn, 0, 13),
54
-GEN_VXFORM_207(bcdadd, 0, 24),
55
-GEN_VXFORM_207(bcdsub, 0, 25),
56
-GEN_VXFORM_300(bcdtrunc, 0, 28),
57
-GEN_VXFORM_300(xpnd04_2, 0, 30),
58
-GEN_VXFORM_300(bcdtrunc, 0, 20),
59
-GEN_VXFORM_300(bcdutrunc, 0, 21),
38
GEN_VXFORM(vsl, 2, 7),
39
GEN_VXFORM(vsr, 2, 11),
40
GEN_VXFORM(vsum4ubs, 4, 24),