hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command
The AST2600 and later crypto engines drive the source and destination through scatter-gather lists (HACE10[18]/[19]) rather than the single contiguous buffers used by the AST2500 direct access mode. Each SG list entry is a length word (SG_LIST_LEN_LAST marks the final entry) followed by a DRAM address, matching the hash engine layout. Add a crypt_prepare_sg() helper that gathers the source into / scatters the destination out of the bounce buffer by walking the SG list, and select it or the existing crypt_prepare_direct() from do_crypt_operation based on HACE10[18], mirroring the hash engine's direct/scatter-gather dispatch. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260811060115.1849266-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Aug 11, 2026 at 06:01 UTC
604cec223c4bf20b8fef7788263b13d13fed3708
1 file changed
+64
-6
hw/misc/aspeed_hace.c
+64
-6
@@ -608,13 +608,58 @@ static bool crypt_prepare_direct(AspeedHACEState *s, uint64_t addr,
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}
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/*
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- * Perform an AES/DES/3DES ECB/CBC operation in direct access mode: the source
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- * and destination are single contiguous buffers (HACE00/HACE04) and the IV/key
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- * come from the context buffer (HACE08). For CBC the resulting chaining IV is
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- * written back to the context buffer so the driver can continue the chain.
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+ * Scatter-gather mode: the source/destination register points at an SG list
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+ * whose entries are a length word (SG_LIST_LEN_LAST flags the final entry)
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+ * followed by a DRAM address, matching the hash engine layout. Gather @len
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+ * bytes into @buf, or scatter @buf back out when @to_dram is true.
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+ * Returns true on success.
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+ */
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+static bool crypt_prepare_sg(AspeedHACEState *s, uint64_t addr,
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+ uint8_t *buf, uint32_t len, bool to_dram)
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+{
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+ uint32_t copied = 0;
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+ uint32_t sg_addr;
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+ uint32_t sg_len;
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+ uint32_t entry;
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+ int i;
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+
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+ for (i = 0; i < ASPEED_HACE_MAX_SG && copied < len; i++) {
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+ entry = address_space_ldl_le(&s->dram_as, addr,
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+ MEMTXATTRS_UNSPECIFIED, NULL);
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+ sg_addr = address_space_ldl_le(&s->dram_as, addr + SG_LIST_LEN_SIZE,
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+ MEMTXATTRS_UNSPECIFIED, NULL);
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+ sg_len = entry & SG_LIST_LEN_MASK;
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+
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+ sg_addr &= SG_LIST_ADDR_MASK;
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+ addr += SG_LIST_ENTRY_SIZE;
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+
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+ if (sg_len > len - copied) {
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+ sg_len = len - copied;
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+ }
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+ if (address_space_rw(&s->dram_as, sg_addr, MEMTXATTRS_UNSPECIFIED,
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+ buf + copied, sg_len, to_dram)) {
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+ return false;
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+ }
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+ copied += sg_len;
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+
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+ if (entry & SG_LIST_LEN_LAST) {
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+ break;
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+ }
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+ }
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+
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+ return copied == len;
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+}
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+
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+/*
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+ * Perform an AES/DES/3DES ECB/CBC operation. The source and destination are
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+ * either single contiguous buffers (direct access mode) or scatter-gather
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+ * lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the IV/key come from
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+ * the context buffer (HACE08). For CBC the resulting chaining IV is written
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+ * back to the context buffer so the driver can continue the chain.
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*/
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static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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{
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+ bool sg_mode = cmd & CRYPT_CMD_SRC_SG_CTRL;
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uint32_t len = s->regs[R_CRYPT_DATA_LEN];
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bool encrypt = cmd & CRYPT_CMD_ENCRYPT;
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g_autoptr(QCryptoCipher) cipher = NULL;
@@ -631,6 +676,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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size_t iv_offset;
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size_t blocklen;
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size_t keylen;
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+ bool status;
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if (len == 0) {
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return;
@@ -684,8 +730,14 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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src_buf = g_malloc0(len);
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dst_buf = g_malloc0(len);
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+ /* Gather the source into the bounce buffer, per the selected mode. */
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src_addr = s->regs[R_CRYPT_SRC];
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- if (!crypt_prepare_direct(s, src_addr, src_buf, len, false)) {
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+ if (sg_mode) {
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+ status = crypt_prepare_sg(s, src_addr, src_buf, len, false);
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+ } else {
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+ status = crypt_prepare_direct(s, src_addr, src_buf, len, false);
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+ }
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+ if (!status) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Failed to read src, addr=0x%" HWADDR_PRIx "\n",
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__func__, src_addr);
@@ -714,8 +766,14 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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}
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}
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+ /* Scatter the result back out, per the selected mode. */
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dst_addr = s->regs[R_CRYPT_DEST];
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- if (!crypt_prepare_direct(s, dst_addr, dst_buf, len, true)) {
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+ if (sg_mode) {
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+ status = crypt_prepare_sg(s, dst_addr, dst_buf, len, true);
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+ } else {
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+ status = crypt_prepare_direct(s, dst_addr, dst_buf, len, true);
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+ }
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+ if (!status) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Failed to write dst, addr=0x%" HWADDR_PRIx "\n",
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__func__, dst_addr);