target/arm: implements SEV/SEVL for all modes
Remove the restrictions that make this a M-profile only operation and enable the instructions for all Arm profiles. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260624103049.884930-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Jun 24, 2026 at 11:30 UTC
60e7ee5bb7cde8a91f196dff0279774cd46ba70a
8 files changed
+59
-18
target/arm/tcg/a32.decode
+2
-3
@@ -192,9 +192,8 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
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WFE ---- 0011 0010 0000 1111 ---- 0000 0010
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WFI ---- 0011 0010 0000 1111 ---- 0000 0011
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- # TODO: Implement SEV, SEVL; may help SMP performance.
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- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
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- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
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+ SEV ---- 0011 0010 0000 1111 ---- 0000 0100
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+ SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
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ESB ---- 0011 0010 0000 1111 ---- 0001 0000
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]
target/arm/tcg/a64.decode
+2
-3
@@ -250,9 +250,8 @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
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YIELD 1101 0101 0000 0011 0010 0000 001 11111
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WFE 1101 0101 0000 0011 0010 0000 010 11111
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WFI 1101 0101 0000 0011 0010 0000 011 11111
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- # We implement WFE to never block, so our SEV/SEVL are NOPs
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- # SEV 1101 0101 0000 0011 0010 0000 100 11111
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- # SEVL 1101 0101 0000 0011 0010 0000 101 11111
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+ SEV 1101 0101 0000 0011 0010 0000 100 11111
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+ SEVL 1101 0101 0000 0011 0010 0000 101 11111
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# Our DGL is a NOP because we don't merge memory accesses anyway.
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# DGL 1101 0101 0000 0011 0010 0000 110 11111
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XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
target/arm/tcg/op_helper.c
+1
-3
@@ -477,9 +477,7 @@ void HELPER(sev)(CPUARMState *env)
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CPUState *cs = env_cpu(env);
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CPU_FOREACH(cs) {
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ARMCPU *target_cpu = ARM_CPU(cs);
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- if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) {
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- target_cpu->env.event_register = true;
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- }
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+ target_cpu->env.event_register = true;
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if (!qemu_cpu_is_self(cs)) {
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qemu_cpu_kick(cs);
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}
target/arm/tcg/t16.decode
+1
-3
@@ -228,10 +228,8 @@ REVSH 1011 1010 11 ... ... @rdm
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WFE 1011 1111 0010 0000
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WFI 1011 1111 0011 0000
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- # M-profile SEV is implemented.
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- # TODO: Implement SEV for other profiles, and SEVL for all profiles; may help SMP performance.
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SEV 1011 1111 0100 0000
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- # SEVL 1011 1111 0101 0000
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+ SEVL 1011 1111 0101 0000
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# The canonical nop has the second nibble as 0000, but the whole of the
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# rest of the space is a reserved hint, behaves as nop.
target/arm/tcg/t32.decode
+1
-3
@@ -369,10 +369,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
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WFE 1111 0011 1010 1111 1000 0000 0000 0010
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WFI 1111 0011 1010 1111 1000 0000 0000 0011
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- # M-profile SEV is implemented.
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- # TODO: Implement SEV for other profiles, and SEVL for all profiles; may help SMP performance.
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SEV 1111 0011 1010 1111 1000 0000 0000 0100
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- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
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+ SEVL 1111 0011 1010 1111 1000 0000 0000 0101
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ESB 1111 0011 1010 1111 1000 0000 0001 0000
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]
target/arm/tcg/translate-a64.c
+17
@@ -2142,6 +2142,23 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
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return true;
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}
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+static bool trans_SEV(DisasContext *s, arg_SEV *a)
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+{
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+ /*
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+ * SEV is a NOP for user-mode emulation.
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+ */
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+#ifndef CONFIG_USER_ONLY
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+ gen_helper_sev(tcg_env);
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+#endif
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+ return true;
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+}
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+
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+static bool trans_SEVL(DisasContext *s, arg_SEV *a)
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+{
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+ gen_event_reg();
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+ return true;
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+}
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+
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static bool trans_WFE(DisasContext *s, arg_WFI *a)
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{
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/*
target/arm/tcg/translate.c
+17
-3
@@ -3246,17 +3246,31 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
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static bool trans_SEV(DisasContext *s, arg_SEV *a)
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{
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/*
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- * Currently SEV is a NOP for non-M-profile and in user-mode emulation.
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- * For system-mode M-profile, it sets the event register.
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+ * SEV is a NOP for user-mode emulation. For v6T2 and earlier
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+ * non-M-profile cores this encoding is a NOP hint.
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*/
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#ifndef CONFIG_USER_ONLY
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- if (arm_dc_feature(s, ARM_FEATURE_M)) {
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+ if (arm_dc_feature(s, ARM_FEATURE_M) ||
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+ arm_dc_feature(s, ARM_FEATURE_V7)) {
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gen_helper_sev(tcg_env);
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}
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#endif
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return true;
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}
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+static bool trans_SEVL(DisasContext *s, arg_SEV *a)
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+{
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+ /*
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+ * SEVL only exists for v8A; for M-profile and v7A and earlier
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+ * this encoding is an unallocated must-NOP hint.
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+ */
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+ if (!arm_dc_feature(s, ARM_FEATURE_M) &&
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+ arm_dc_feature(s, ARM_FEATURE_V8)) {
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+ gen_event_reg();
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+ }
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+ return true;
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+}
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+
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static bool trans_WFE(DisasContext *s, arg_WFE *a)
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{
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/*
target/arm/tcg/translate.h
+18
@@ -860,6 +860,24 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
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gen_helper_set_rmode(old, old, fpst);
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}
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+/*
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+ * Event Register signalling.
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+ *
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+ * A bunch of activities trigger events, we just need to latch on to
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+ * true. The event eventually gets consumed by WFE/WFET.
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+ *
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+ * user-mode treats these as NOPs.
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+ */
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+
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+static inline void gen_event_reg(void)
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+{
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+#ifndef CONFIG_USER_ONLY
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+ TCGv_i32 set_event = tcg_constant_i32(1);
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+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, event_register) != 1);
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+ tcg_gen_st8_i32(set_event, tcg_env, offsetof(CPUARMState, event_register));
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+#endif
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+}
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+
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/*
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* Helpers for implementing sets of trans_* functions.
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* Defer the implementation of NAME to FUNC, with optional extra arguments.