hw/i3c/dw-i3c: Add ctrl MMIO handling
Adds functionality to the CTRL register. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-16-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
61c2a72bbc1ba293e4b0121a30a4953371af22ab
1 file changed
+35
hw/i3c/dw-i3c.c
+35
@@ -344,6 +344,8 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = {
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[R_SLAVE_CONFIG] = 0xffffffff,
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};
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+static void dw_i3c_cmd_queue_execute(DWI3C *s);
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+
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static inline bool dw_i3c_has_hdr_ts(DWI3C *s)
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{
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return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS);
@@ -503,6 +505,36 @@ static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data,
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return ret;
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}
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+static void dw_i3c_ctrl_w(DWI3C *s, uint32_t val)
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+{
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+ /*
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+ * If the user is setting I3C_RESUME, the controller was halted.
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+ * Try and resume execution and leave the bit cleared.
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+ */
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+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) {
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+ dw_i3c_cmd_queue_execute(s);
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+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0);
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+ }
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+ /*
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+ * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is
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+ * sent.
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+ */
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+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) {
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+ dw_i3c_end_transfer(s, /*is_i2c=*/true);
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+ dw_i3c_end_transfer(s, /*is_i2c=*/false);
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+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0);
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+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1);
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+ dw_i3c_update_irq(s);
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+ }
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+ /* Update present state. */
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+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,
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+ DW_I3C_TRANSFER_STATE_IDLE);
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+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,
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+ DW_I3C_TRANSFER_STATUS_IDLE);
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+
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+ s->regs[R_DEVICE_CTRL] = val;
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+}
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+
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static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset)
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{
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/* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */
@@ -1575,6 +1607,9 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
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"] = 0x%08" PRIx64 "\n",
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__func__, offset, value);
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break;
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+ case R_DEVICE_CTRL:
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+ dw_i3c_ctrl_w(s, val32);
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+ break;
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case R_RX_TX_DATA_PORT:
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dw_i3c_push_tx(s, val32);
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break;