@samitouri / QOSamiQemu / commits / 63469ad75d

target/riscv: Fix arguments to board IMSIC emulation callbacks

In hw/ the relevant RISCVIMSICState fields eidelivery, eithreshold, eistate are uint32_t. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-16-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Anton Johansson committed May 20, 2026 at 14:53 UTC 63469ad75dcc17849a29ad115ec3711d72308eeb
4 files changed +57 -55
hw/intc/riscv_imsic.c
+17 -17
@@ -88,11 +88,11 @@ static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
88 }
89
90 static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
91 - target_ulong *val,
92 - target_ulong new_val,
93 - target_ulong wr_mask)
91 + uint64_t *val,
92 + uint64_t new_val,
93 + uint64_t wr_mask)
94 {
95 - target_ulong old_val = imsic->eidelivery[page];
95 + uint32_t old_val = imsic->eidelivery[page];
96
97 if (val) {
98 *val = old_val;
@@ -106,11 +106,11 @@ static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
106 }
107
108 static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
109 - target_ulong *val,
110 - target_ulong new_val,
111 - target_ulong wr_mask)
109 + uint64_t *val,
110 + uint64_t new_val,
111 + uint64_t wr_mask)
112 {
113 - target_ulong old_val = imsic->eithreshold[page];
113 + uint32_t old_val = imsic->eithreshold[page];
114
115 if (val) {
116 *val = old_val;
@@ -124,8 +124,8 @@ static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
124 }
125
126 static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
127 - target_ulong *val, target_ulong new_val,
128 - target_ulong wr_mask)
127 + uint64_t *val, uint64_t new_val,
128 + uint64_t wr_mask)
129 {
130 uint32_t base, topei = riscv_imsic_topei(imsic, page);
131
@@ -149,11 +149,11 @@ static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
149
150 static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
151 uint32_t xlen, uint32_t page,
152 - uint32_t num, bool pend, target_ulong *val,
153 - target_ulong new_val, target_ulong wr_mask)
152 + uint32_t num, bool pend, uint64_t *val,
153 + uint64_t new_val, uint64_t wr_mask)
154 {
155 uint32_t i, base, prev;
156 - target_ulong mask;
156 + uint64_t mask;
157 uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
158
159 if (xlen != 32) {
@@ -178,7 +178,7 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
178 continue;
179 }
180
181 - mask = (target_ulong)1 << i;
181 + mask = 1ull << i;
182 if (wr_mask & mask) {
183 if (new_val & mask) {
184 prev = qatomic_fetch_or(&imsic->eistate[base + i], state);
@@ -197,8 +197,8 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
197 return 0;
198 }
199
200 -static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val,
201 - target_ulong new_val, target_ulong wr_mask)
200 +static int riscv_imsic_rmw(void *arg, uint32_t reg, uint64_t *val,
201 + uint64_t new_val, uint64_t wr_mask)
202 {
203 RISCVIMSICState *imsic = arg;
204 uint32_t isel, priv, virt, vgein, xlen, page;
@@ -400,7 +400,7 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
400 }
401
402 if (!kvm_irqchip_in_kernel()) {
403 - riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
403 + riscv_cpu_set_aia_ireg_rmw_cb(env, (imsic->mmode) ? PRV_M : PRV_S,
404 riscv_imsic_rmw, imsic);
405 }
406 }
target/riscv/cpu.h
+22 -20
@@ -201,6 +201,24 @@ FIELD(VTYPE, VMA, 7, 1)
201 FIELD(VTYPE, ALTFMT, 8, 1)
202 FIELD(VTYPE, RESERVED, 9, sizeof(uint64_t) * 8 - 10)
203
204 +#ifndef CONFIG_USER_ONLY
205 +/* machine specific AIA ireg read-modify-write callback */
206 +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
207 + ((uint32_t)((((__xlen) & 0xff) << 24) | \
208 + (((__vgein) & 0x3f) << 20) | \
209 + (((__virt) & 0x1) << 18) | \
210 + (((__priv) & 0x3) << 16) | \
211 + (__isel & 0xffff)))
212 +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
213 +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
214 +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
215 +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
216 +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
217 +
218 +typedef int (*aia_ireg_rmw_fn)(void *arg, uint32_t reg, uint64_t *val,
219 + uint64_t new_val, uint64_t write_mask);
220 +#endif
221 +
222 typedef struct PMUCTRState {
223 /* Current value of a counter */
224 uint64_t mhpmcounter_val;
@@ -466,20 +484,8 @@ struct CPUArchState {
484 void *rdtime_fn_arg;
485
486 /* machine specific AIA ireg read-modify-write callback */
469 -#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
470 - ((((__xlen) & 0xff) << 24) | \
471 - (((__vgein) & 0x3f) << 20) | \
472 - (((__virt) & 0x1) << 18) | \
473 - (((__priv) & 0x3) << 16) | \
474 - (__isel & 0xffff))
475 -#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
476 -#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
477 -#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
478 -#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
479 -#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
480 - int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
481 - target_ulong *val, target_ulong new_val, target_ulong write_mask);
482 - void *aia_ireg_rmw_fn_arg[4];
487 + aia_ireg_rmw_fn aia_ireg_rmw_cb[4];
488 + void *aia_ireg_rmw_cb_arg[4];
489
490 /* True if in debugger mode. */
491 bool debugger;
@@ -648,12 +654,8 @@ void riscv_cpu_interrupt(CPURISCVState *env);
654 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
655 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
656 void *arg);
651 -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t priv,
652 - int (*rmw_fn)(void *arg,
653 - target_ulong reg,
654 - target_ulong *val,
655 - target_ulong new_val,
656 - target_ulong write_mask),
657 +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
658 + aia_ireg_rmw_fn rmw_fn,
659 void *rmw_fn_arg);
660
661 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
target/riscv/cpu_helper.c
+4 -8
@@ -816,17 +816,13 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
816 env->rdtime_fn_arg = arg;
817 }
818
819 -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t priv,
820 - int (*rmw_fn)(void *arg,
821 - target_ulong reg,
822 - target_ulong *val,
823 - target_ulong new_val,
824 - target_ulong write_mask),
819 +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
820 + aia_ireg_rmw_fn rmw_fn,
821 void *rmw_fn_arg)
822 {
823 if (priv <= PRV_M) {
828 - env->aia_ireg_rmw_fn[priv] = rmw_fn;
829 - env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
824 + env->aia_ireg_rmw_cb[priv] = rmw_fn;
825 + env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg;
826 }
827 }
828
target/riscv/csr.c
+14 -10
@@ -2673,6 +2673,7 @@ static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
2673 uint8_t *iprio;
2674 privilege_mode_t priv;
2675 uint32_t vgein;
2676 + uint64_t wide_val;
2677
2678 /* VS-mode CSR number passed in has already been translated */
2679 switch (csrno) {
@@ -2717,16 +2718,17 @@ static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
2718 }
2719 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
2720 /* IMSIC registers only available when machine implements it. */
2720 - if (env->aia_ireg_rmw_fn[priv]) {
2721 + if (env->aia_ireg_rmw_cb[priv]) {
2722 /* Selected guest interrupt file should not be zero */
2723 if (virt && (!vgein || env->geilen < vgein)) {
2724 goto done;
2725 }
2726 /* Call machine specific IMSIC register emulation */
2726 - ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
2727 + ret = env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv],
2728 AIA_MAKE_IREG(isel, priv, virt, vgein,
2729 riscv_cpu_mxl_bits(env)),
2729 - val, new_val, wr_mask);
2730 + &wide_val, new_val, wr_mask);
2731 + *val = wide_val;
2732 }
2733 } else {
2734 isel_reserved = true;
@@ -2959,6 +2961,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
2961 int ret = -EINVAL;
2962 privilege_mode_t priv;
2963 uint32_t vgein;
2964 + uint64_t wide_val;
2965
2966 /* Translate CSR number for VS-mode */
2967 csrno = aia_xlate_vs_csrno(env, csrno);
@@ -2984,7 +2987,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
2987 };
2988
2989 /* IMSIC CSRs only available when machine implements IMSIC. */
2987 - if (!env->aia_ireg_rmw_fn[priv]) {
2990 + if (!env->aia_ireg_rmw_cb[priv]) {
2991 goto done;
2992 }
2993
@@ -2997,10 +3000,11 @@ static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
3000 }
3001
3002 /* Call machine specific IMSIC register emulation for TOPEI */
3000 - ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
3003 + ret = env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv],
3004 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
3005 riscv_cpu_mxl_bits(env)),
3003 - val, new_val, wr_mask);
3006 + &wide_val, new_val, wr_mask);
3007 + *val = wide_val;
3008
3009 done:
3010 if (ret) {
@@ -4504,7 +4508,7 @@ static RISCVException read_vstopi(CPURISCVState *env, int csrno,
4508 target_ulong *val)
4509 {
4510 int irq, ret;
4507 - target_ulong topei;
4511 + uint64_t topei = 0;
4512 uint64_t vseip, vsgein;
4513 uint32_t iid, iprio, hviid, hviprio, gein;
4514 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
@@ -4519,13 +4523,13 @@ static RISCVException read_vstopi(CPURISCVState *env, int csrno,
4523 if (gein <= env->geilen && vseip) {
4524 siid[scount] = IRQ_S_EXT;
4525 siprio[scount] = IPRIO_MMAXIPRIO + 1;
4522 - if (env->aia_ireg_rmw_fn[PRV_S]) {
4526 + if (env->aia_ireg_rmw_cb[PRV_S]) {
4527 /*
4528 * Call machine specific IMSIC register emulation for
4529 * reading TOPEI.
4530 */
4527 - ret = env->aia_ireg_rmw_fn[PRV_S](
4528 - env->aia_ireg_rmw_fn_arg[PRV_S],
4531 + ret = env->aia_ireg_rmw_cb[PRV_S](
4532 + env->aia_ireg_rmw_cb_arg[PRV_S],
4533 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
4534 riscv_cpu_mxl_bits(env)),
4535 &topei, 0, 0);