target/riscv: De-indent some code in get_physical_address()
get_physical_address() is quite complex already. In order to make the two next commits simplers, de-indent one if() ladder. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-5-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
May 27, 2026 at 22:13 UTC
64d3884bbfe9b7abef2919bc3f0234afec7a1866
1 file changed
+18
-15
target/riscv/cpu_helper.c
+18
-15
@@ -1667,27 +1667,30 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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hwaddr l = sxlen_bytes, addr1;
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mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
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false, MEMTXATTRS_UNSPECIFIED);
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- if (memory_region_is_ram(mr)) {
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- target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
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- target_ulong old_pte;
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- if (riscv_cpu_sxl(env) == MXL_RV32) {
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- old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pte), cpu_to_le32(updated_pte));
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- old_pte = le32_to_cpu(old_pte);
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- } else {
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- old_pte = qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_to_le64(updated_pte));
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- old_pte = le64_to_cpu(old_pte);
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- }
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- if (old_pte != pte) {
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- goto restart;
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- }
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- pte = updated_pte;
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- } else {
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+ if (!memory_region_is_ram(mr)) {
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/*
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* Misconfigured PTE in ROM (AD bits are not preset) or
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* PTE is in IO space and can't be updated atomically.
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*/
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return TRANSLATE_FAIL;
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}
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+
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+ target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
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+ target_ulong old_pte;
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+
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+ if (riscv_cpu_sxl(env) == MXL_RV32) {
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+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pte),
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+ cpu_to_le32(updated_pte));
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+ old_pte = le32_to_cpu(old_pte);
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+ } else {
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+ old_pte = qatomic_cmpxchg(pte_pa, cpu_to_le64(pte),
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+ cpu_to_le64(updated_pte));
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+ old_pte = le64_to_cpu(old_pte);
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+ }
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+ if (old_pte != pte) {
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+ goto restart;
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+ }
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+ pte = updated_pte;
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}
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/* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */