hw/ssi/xilinx_spips: Reset TX FIFO in reset
In xilinx_spips_reset() and xlnx_zynqmp_qspips_reset() a cut and paste error meant we reset the RX FIFO twice and the TX FIFO not at all. Correct this to reset both FIFOs. Cc: qemu-stable@nongnu.org Signed-off-by: Weixie Cui <cuiweixie@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260223095905.67709-1-cuiweixie@gmail.com [Rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Weixie Cui committed
Feb 26, 2026 at 11:27 UTC
669683cf1414ce442d2faea160dbc69747aef007
1 file changed
+2
-2
hw/ssi/xilinx_spips.c
+2
-2
@@ -369,7 +369,7 @@ static void xilinx_spips_reset(DeviceState *d)
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memset(s->regs, 0, sizeof(s->regs));
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fifo8_reset(&s->rx_fifo);
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- fifo8_reset(&s->rx_fifo);
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+ fifo8_reset(&s->tx_fifo);
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/* non zero resets */
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s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
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s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
@@ -397,7 +397,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
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memset(s->regs, 0, sizeof(s->regs));
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fifo8_reset(&s->rx_fifo_g);
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- fifo8_reset(&s->rx_fifo_g);
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+ fifo8_reset(&s->tx_fifo_g);
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fifo32_reset(&s->fifo_g);
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s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
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s->regs[R_GPIO] = 1;