virtio-gpu: Support asynchronous fencing
Support asynchronous fencing feature of virglrenderer. It allows Qemu to handle fence as soon as it's signalled instead of periodically polling the fence status. This feature is required for enabling DRM context support in Qemu because legacy fencing mode isn't supported for DRM contexts in virglrenderer. Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Yiwei Zhang <zzyiwei@gmail.com> Tested-by: Yiwei Zhang <zzyiwei@gmail.com> Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Message-ID: <20260303151422.977399-10-dmitry.osipenko@collabora.com> Message-ID: <20260304165043.1437519-12-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Dmitry Osipenko committed
Mar 4, 2026 at 16:50 UTC
6698eae8a1f6d897ea0ad62e47448c296eec0bf9
4 files changed
+145
hw/display/virtio-gpu-gl.c
+5
@@ -169,6 +169,11 @@ static void virtio_gpu_gl_device_unrealize(DeviceState *qdev)
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if (gl->renderer_state >= RS_INITED) {
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#if VIRGL_VERSION_MAJOR >= 1
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qemu_bh_delete(gl->cmdq_resume_bh);
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+
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+ if (gl->async_fence_bh) {
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+ virtio_gpu_virgl_reset_async_fences(g);
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+ qemu_bh_delete(gl->async_fence_bh);
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+ }
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#endif
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if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
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timer_free(gl->print_stats);
hw/display/virtio-gpu-virgl.c
+127
@@ -24,6 +24,23 @@
24
25
#include <virglrenderer.h>
26
27
+/*
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+ * VIRGL_CHECK_VERSION available since libvirglrenderer 1.0.1 and was fixed
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+ * in 1.1.0. Undefine bugged version of the macro and provide our own.
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+ */
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+#if defined(VIRGL_CHECK_VERSION) && \
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+ VIRGL_VERSION_MAJOR == 1 && VIRGL_VERSION_MINOR < 1
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+#undef VIRGL_CHECK_VERSION
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+#endif
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+
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+#ifndef VIRGL_CHECK_VERSION
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+#define VIRGL_CHECK_VERSION(major, minor, micro) \
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+ (VIRGL_VERSION_MAJOR > (major) || \
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+ VIRGL_VERSION_MAJOR == (major) && VIRGL_VERSION_MINOR > (minor) || \
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+ VIRGL_VERSION_MAJOR == (major) && VIRGL_VERSION_MINOR == (minor) && \
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+ VIRGL_VERSION_MICRO >= (micro))
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+#endif
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+
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struct virtio_gpu_virgl_resource {
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struct virtio_gpu_simple_resource base;
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MemoryRegion *mr;
@@ -1079,6 +1096,103 @@ static void virgl_write_context_fence(void *opaque, uint32_t ctx_id,
1096
}
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#endif
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1099
+void virtio_gpu_virgl_reset_async_fences(VirtIOGPU *g)
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+{
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+ struct virtio_gpu_virgl_context_fence *f;
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+ VirtIOGPUGL *gl = VIRTIO_GPU_GL(g);
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+
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+ while (!QSLIST_EMPTY(&gl->async_fenceq)) {
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+ f = QSLIST_FIRST(&gl->async_fenceq);
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+
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+ QSLIST_REMOVE_HEAD(&gl->async_fenceq, next);
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+
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+ g_free(f);
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+ }
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+}
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+
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+#if VIRGL_CHECK_VERSION(1, 1, 2)
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+static void virtio_gpu_virgl_async_fence_bh(void *opaque)
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+{
1116
+ QSLIST_HEAD(, virtio_gpu_virgl_context_fence) async_fenceq;
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+ struct virtio_gpu_ctrl_command *cmd, *tmp;
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+ struct virtio_gpu_virgl_context_fence *f;
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+ VirtIOGPU *g = opaque;
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+ VirtIOGPUGL *gl = VIRTIO_GPU_GL(g);
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+
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+ if (gl->renderer_state != RS_INITED) {
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+ return;
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+ }
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+
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+ QSLIST_MOVE_ATOMIC(&async_fenceq, &gl->async_fenceq);
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+
1128
+ while (!QSLIST_EMPTY(&async_fenceq)) {
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+ f = QSLIST_FIRST(&async_fenceq);
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+
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+ QSLIST_REMOVE_HEAD(&async_fenceq, next);
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+
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+ QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
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+ /*
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+ * the guest can end up emitting fences out of order
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+ * so we should check all fenced cmds not just the first one.
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+ */
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+ if (cmd->cmd_hdr.fence_id > f->fence_id) {
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+ continue;
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+ }
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+ if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX) {
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+ if (cmd->cmd_hdr.ring_idx != f->ring_idx) {
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+ continue;
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+ }
1145
+ if (cmd->cmd_hdr.ctx_id != f->ctx_id) {
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+ continue;
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+ }
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+ }
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+ virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
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+ QTAILQ_REMOVE(&g->fenceq, cmd, next);
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+ g_free(cmd);
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+ }
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+
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+ trace_virtio_gpu_fence_resp(f->fence_id);
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+ g_free(f);
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+ g->inflight--;
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+ if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
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+ trace_virtio_gpu_dec_inflight_fences(g->inflight);
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+ }
1160
+ }
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+}
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+
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+static void
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+virtio_gpu_virgl_push_async_fence(VirtIOGPU *g, uint32_t ctx_id,
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+ uint32_t ring_idx, uint64_t fence_id)
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+{
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+ struct virtio_gpu_virgl_context_fence *f;
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+ VirtIOGPUGL *gl = VIRTIO_GPU_GL(g);
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+
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+ f = g_new(struct virtio_gpu_virgl_context_fence, 1);
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+ f->ctx_id = ctx_id;
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+ f->ring_idx = ring_idx;
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+ f->fence_id = fence_id;
1174
+
1175
+ QSLIST_INSERT_HEAD_ATOMIC(&gl->async_fenceq, f, next);
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+
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+ qemu_bh_schedule(gl->async_fence_bh);
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+}
1179
+
1180
+static void virgl_write_async_fence(void *opaque, uint32_t fence)
1181
+{
1182
+ VirtIOGPU *g = opaque;
1183
+
1184
+ virtio_gpu_virgl_push_async_fence(g, 0, UINT32_MAX, fence);
1185
+}
1186
+
1187
+static void virgl_write_async_context_fence(void *opaque, uint32_t ctx_id,
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+ uint32_t ring_idx, uint64_t fence)
1189
+{
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+ VirtIOGPU *g = opaque;
1191
+
1192
+ virtio_gpu_virgl_push_async_fence(g, ctx_id, ring_idx, fence);
1193
+}
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+#endif
1195
+
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static virgl_renderer_gl_context
1197
virgl_create_context(void *opaque, int scanout_idx,
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struct virgl_renderer_gl_ctx_param *params)
@@ -1178,6 +1292,8 @@ void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g)
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void virtio_gpu_virgl_reset(VirtIOGPU *g)
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{
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virgl_renderer_reset();
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+
1296
+ virtio_gpu_virgl_reset_async_fences(g);
1297
}
1298
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int virtio_gpu_virgl_init(VirtIOGPU *g)
@@ -1190,6 +1306,12 @@ int virtio_gpu_virgl_init(VirtIOGPU *g)
1306
if (qemu_egl_display) {
1307
virtio_gpu_3d_cbs.version = 4;
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virtio_gpu_3d_cbs.get_egl_display = virgl_get_egl_display;
1309
+#if VIRGL_CHECK_VERSION(1, 1, 2)
1310
+ virtio_gpu_3d_cbs.write_fence = virgl_write_async_fence;
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+ virtio_gpu_3d_cbs.write_context_fence = virgl_write_async_context_fence;
1312
+ flags |= VIRGL_RENDERER_ASYNC_FENCE_CB;
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+ flags |= VIRGL_RENDERER_THREAD_SYNC;
1314
+#endif
1315
}
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#endif
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#ifdef VIRGL_RENDERER_D3D11_SHARE_TEXTURE
@@ -1223,6 +1345,11 @@ int virtio_gpu_virgl_init(VirtIOGPU *g)
1345
gl->cmdq_resume_bh = virtio_bh_io_new_guarded(DEVICE(g),
1346
virtio_gpu_virgl_resume_cmdq_bh,
1347
g);
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+#if VIRGL_CHECK_VERSION(1, 1, 2)
1349
+ gl->async_fence_bh = virtio_bh_io_new_guarded(DEVICE(g),
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+ virtio_gpu_virgl_async_fence_bh,
1351
+ g);
1352
+#endif
1353
#endif
1354
1355
return 0;
include/hw/virtio/virtio-gpu.h
+11
@@ -233,6 +233,13 @@ struct VirtIOGPUClass {
233
Error **errp);
234
};
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+struct virtio_gpu_virgl_context_fence {
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+ uint32_t ctx_id;
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+ uint32_t ring_idx;
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+ uint64_t fence_id;
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+ QSLIST_ENTRY(virtio_gpu_virgl_context_fence) next;
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+};
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+
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/* VirtIOGPUGL renderer states */
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typedef enum {
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RS_START, /* starting state */
@@ -250,6 +257,9 @@ struct VirtIOGPUGL {
257
QEMUTimer *print_stats;
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259
QEMUBH *cmdq_resume_bh;
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+
261
+ QEMUBH *async_fence_bh;
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+ QSLIST_HEAD(, virtio_gpu_virgl_context_fence) async_fenceq;
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};
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struct VhostUserGPU {
@@ -380,5 +390,6 @@ void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g);
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void virtio_gpu_virgl_reset(VirtIOGPU *g);
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int virtio_gpu_virgl_init(VirtIOGPU *g);
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GArray *virtio_gpu_virgl_get_capsets(VirtIOGPU *g);
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+void virtio_gpu_virgl_reset_async_fences(VirtIOGPU *g);
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#endif
meson.build
+2
@@ -2524,6 +2524,8 @@ config_host_data.set('CONFIG_VNC_JPEG', jpeg.found())
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config_host_data.set('CONFIG_VNC_SASL', sasl.found())
2525
if virgl.found()
2526
config_host_data.set('VIRGL_VERSION_MAJOR', virgl.version().split('.')[0])
2527
+ config_host_data.set('VIRGL_VERSION_MINOR', virgl.version().split('.')[1])
2528
+ config_host_data.set('VIRGL_VERSION_MICRO', virgl.version().split('.')[2])
2529
endif
2530
config_host_data.set('CONFIG_VIRTFS', have_virtfs)
2531
config_host_data.set('CONFIG_VTE', vte.found())