target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree
Moving the following instructions to decodetree specification: mfmsr : X-form mtmsr[d] : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Gate MFMSR/MTMSR on PPC_MISC via TRANS_FLAGS() - Use UINT32_MAX instead of 0xFFFFFFFF for clarity Signed-off-by: Vishal Chourasia <vishalc@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-28-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Vishal Chourasia committed
Aug 27, 2026 at 18:59 UTC
67257829f046eeeffbc08c53349cbc3f9c4f1902
3 files changed
+69
-97
target/ppc/insn32.decode
+5
@@ -315,6 +315,11 @@
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&M ra rs sh mb me rc:bool
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@M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M
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+### MSR
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+MFMSR 011111 ..... ----- ----- 0001010011 - @X_t
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+MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l
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+MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l
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+
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### Fixed-Point Load Instructions
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LBZ 100010 ..... ..... ................ @D
target/ppc/translate.c
-97
@@ -2843,13 +2843,6 @@ static void gen_mcrxrx(DisasContext *ctx)
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}
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#endif
2845
2846
-/* mfmsr */
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-static void gen_mfmsr(DisasContext *ctx)
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-{
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- CHK_SV(ctx);
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- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
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-}
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-
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/* mfspr */
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static inline void gen_op_mfspr(DisasContext *ctx)
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{
@@ -2923,93 +2916,6 @@ static void gen_mftb(DisasContext *ctx)
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gen_op_mfspr(ctx);
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}
2918
2926
-/* mtmsr */
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-#if defined(TARGET_PPC64)
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-static void gen_mtmsrd(DisasContext *ctx)
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-{
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- if (unlikely(!is_book3s_arch2x(ctx))) {
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- gen_invalid(ctx);
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- return;
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- }
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-
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- CHK_SV(ctx);
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-
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-#if !defined(CONFIG_USER_ONLY)
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- TCGv t0, t1;
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- target_ulong mask;
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-
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- t0 = tcg_temp_new();
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- t1 = tcg_temp_new();
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-
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- translator_io_start(&ctx->base);
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-
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- if (ctx->opcode & 0x00010000) {
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- /* L=1 form only updates EE and RI */
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- mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
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- } else {
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- /* mtmsrd does not alter HV, S, ME, or LE */
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- mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
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- (1ULL << MSR_HV));
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- /*
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- * XXX: we need to update nip before the store if we enter
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- * power saving mode, we will exit the loop directly from
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- * ppc_store_msr
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- */
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- gen_update_nip(ctx, ctx->base.pc_next);
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- }
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-
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- tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
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- tcg_gen_andi_tl(t1, cpu_msr, ~mask);
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- tcg_gen_or_tl(t0, t0, t1);
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-
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- gen_helper_store_msr(tcg_env, t0);
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-
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- /* Must stop the translation as machine state (may have) changed */
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- ctx->base.is_jmp = DISAS_EXIT_UPDATE;
2969
-#endif /* !defined(CONFIG_USER_ONLY) */
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-}
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-#endif /* defined(TARGET_PPC64) */
2972
-
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-static void gen_mtmsr(DisasContext *ctx)
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-{
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- CHK_SV(ctx);
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-
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-#if !defined(CONFIG_USER_ONLY)
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- TCGv t0, t1;
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- target_ulong mask = 0xFFFFFFFF;
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-
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- t0 = tcg_temp_new();
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- t1 = tcg_temp_new();
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-
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- translator_io_start(&ctx->base);
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- if (ctx->opcode & 0x00010000) {
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- /* L=1 form only updates EE and RI */
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- mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
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- } else {
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- if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) {
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- /* mtmsr does not alter S, ME, or LE */
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- mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
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- }
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-
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- /*
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- * XXX: we need to update nip before the store if we enter
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- * power saving mode, we will exit the loop directly from
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- * ppc_store_msr
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- */
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- gen_update_nip(ctx, ctx->base.pc_next);
3000
- }
3001
-
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- tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
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- tcg_gen_andi_tl(t1, cpu_msr, ~mask);
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- tcg_gen_or_tl(t0, t0, t1);
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-
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- gen_helper_store_msr(tcg_env, t0);
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-
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- /* Must stop the translation as machine state (may have) changed */
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- ctx->base.is_jmp = DISAS_EXIT_UPDATE;
3010
-#endif
3011
-}
3012
-
2919
/* mtspr */
2920
static void gen_mtspr(DisasContext *ctx)
2921
{
@@ -4674,15 +4580,12 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
4580
GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
4581
GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
4582
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
4677
-GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
4583
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
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GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
4585
#if defined(TARGET_PPC64)
4681
-GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
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GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
4587
GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
4588
#endif
4685
-GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
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GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
4590
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
4591
GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
target/ppc/translate/misc-impl.c.inc
+64
@@ -161,3 +161,67 @@ static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a)
161
tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]);
162
return true;
163
}
164
+
165
+static bool do_mfmsr(DisasContext *ctx, arg_X_t *a)
166
+{
167
+ REQUIRE_SV(ctx);
168
+ tcg_gen_mov_tl(cpu_gpr[a->rt], cpu_msr);
169
+ return true;
170
+}
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+TRANS_FLAGS(MISC, MFMSR, do_mfmsr)
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+
173
+static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a, bool is_mtmsrd)
174
+{
175
+ REQUIRE_SV(ctx);
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+#if !defined(CONFIG_USER_ONLY)
177
+ TCGv t0, t1;
178
+ target_ulong mask;
179
+
180
+ if (is_mtmsrd) {
181
+ if (unlikely(!is_book3s_arch2x(ctx))) {
182
+ gen_invalid(ctx);
183
+ return true;
184
+ }
185
+ mask = ~(target_ulong)0;
186
+ } else {
187
+ mask = UINT32_MAX;
188
+ }
189
+
190
+ t0 = tcg_temp_new();
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+ t1 = tcg_temp_new();
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+ translator_io_start(&ctx->base);
193
+
194
+ if (a->l) {
195
+ /* L=1 form only updates EE and RI */
196
+ mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
197
+ } else {
198
+ if (is_mtmsrd) {
199
+ /* mtmsrd does not alter HV, S, ME, or LE */
200
+ mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) |
201
+ (1ULL << MSR_S) | (1ULL << MSR_HV));
202
+ } else if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) {
203
+ /* mtmsr does not alter S, ME, or LE */
204
+ mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
205
+ }
206
+ /*
207
+ * XXX: we need to update nip before the store if we enter
208
+ * power saving mode, we will exit the loop directly from
209
+ * ppc_store_msr
210
+ */
211
+ gen_update_nip(ctx, ctx->base.pc_next);
212
+ }
213
+
214
+ tcg_gen_andi_tl(t0, cpu_gpr[a->rs], mask);
215
+ tcg_gen_andi_tl(t1, cpu_msr, ~mask);
216
+ tcg_gen_or_tl(t0, t0, t1);
217
+
218
+ gen_helper_store_msr(tcg_env, t0);
219
+
220
+ /* Must stop the translation as machine state (may have) changed */
221
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
222
+#endif /* !CONFIG_USER_ONLY */
223
+ return true;
224
+}
225
+
226
+TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false)
227
+TRANS64(MTMSRD, do_mtmsr, true)