target/arm: Update SCTLR bits for FEAT_FPMR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
672f2ace5d8fd44e2b4a4116044f52992a758abb
1 file changed
+1
target/arm/cpu.h
+1
@@ -1485,6 +1485,7 @@ void pmu_init(ARMCPU *cpu);
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#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
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#define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
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#define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
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+#define SCTLR_EnFPM (1ULL << 34) /* FEAT_FPMR */
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#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
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#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
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#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */