@samitouri / QOSamiQemu / commits / 67dc6a4c91

hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT

Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. For each accelerated SMMUv3 instance, add a Tegra241 CMDQV device object under the DSDT \_SB namespace, with HID "NVDA200C" and a UID that matches the Identifier of the corresponding SMMUv3 IORT node, so the guest OS can associate the DSDT device with the right SMMU. The _CRS covers the CMDQV MMIO aperture plus its interrupt, and _CCA declares I/O cache coherency. See ACPI Specification 6.5, Section 6 (Device Configuration) for _HID/_UID/_CCA/_CRS. Generated DSDT entry for a CMDQV instance paired with SMMUv3 Identifier=1: ... Device (CV01) { Name (_HID, "NVDA200C") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x0000000000000000, // Granularity 0x000000000C080000, // Range Minimum 0x000000000C0CFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000050000, // Length ,, , AddressRangeMemory, TypeStatic) Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) { 0x00000094, } }) } ... Generated IORT SMMUv3 node (Identifier = 1): ... [048h 0072 001h] Type : 04 [049h 0073 002h] Length : 0058 [04Bh 0075 001h] Revision : 04 [04Ch 0076 004h] Identifier : 00000001 [050h 0080 004h] Mapping Count : 00000001 [054h 0084 004h] Mapping Offset : 00000044 ... Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260609112552.378999-29-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Nicolin Chen committed Jun 9, 2026 at 12:25 UTC 67dc6a4c911b5f3a82766d27f41c5cf60b9c17d4
2 files changed +53
hw/arm/trace-events
+1
@@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s"
9
10 # virt-acpi-build.c
11 virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
12 +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "DSDT: add cmdqv node for (id=%d), base=0x%" PRIx64 ", irq=%d"
13
14 # smmu-common.c
15 smmu_add_mr(const char *name) "%s"
hw/arm/virt-acpi-build.c
+52
@@ -65,6 +65,9 @@
65 #include "target/arm/cpu.h"
66 #include "target/arm/multiprocessing.h"
67
68 +#include "smmuv3-accel.h"
69 +#include "tegra241-cmdqv.h"
70 +
71 #define ARM_SPI_BASE 32
72
73 #define ACPI_BUILD_TABLE_SIZE 0x20000
@@ -1121,6 +1124,51 @@ static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
1124 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
1125 }
1126
1127 +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms)
1128 +{
1129 + for (int i = 0; i < vms->smmuv3_devices->len; i++) {
1130 + Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));
1131 + PlatformBusDevice *pbus;
1132 + Aml *dev, *crs, *addr;
1133 + SysBusDevice *sbdev;
1134 + hwaddr base;
1135 + uint32_t id;
1136 + int irq;
1137 +
1138 + if (smmuv3_accel_cmdqv_type(obj) != SMMUV3_CMDQV_TEGRA241) {
1139 + continue;
1140 + }
1141 + id = object_property_get_uint(obj, "identifier", &error_abort);
1142 + pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
1143 + sbdev = SYS_BUS_DEVICE(obj);
1144 + base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
1145 + base += vms->memmap[VIRT_PLATFORM_BUS].base;
1146 + irq = platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS);
1147 + irq += vms->irqmap[VIRT_PLATFORM_BUS];
1148 + irq += ARM_SPI_BASE;
1149 +
1150 + dev = aml_device("CV%.02u", id);
1151 + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C")));
1152 + aml_append(dev, aml_name_decl("_UID", aml_int(id)));
1153 + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
1154 +
1155 + crs = aml_resource_template();
1156 + addr = aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1157 + AML_CACHEABLE, AML_READ_WRITE, 0x0, base,
1158 + base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0,
1159 + TEGRA241_CMDQV_IO_LEN);
1160 + aml_append(crs, addr);
1161 + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE,
1162 + AML_ACTIVE_HIGH, AML_EXCLUSIVE,
1163 + (uint32_t *)&irq, 1));
1164 + aml_append(dev, aml_name_decl("_CRS", crs));
1165 +
1166 + aml_append(scope, dev);
1167 +
1168 + trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq);
1169 + }
1170 +}
1171 +
1172 /* DSDT */
1173 static void
1174 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
@@ -1185,6 +1233,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
1233 acpi_dsdt_add_tpm(scope, vms);
1234 #endif
1235
1236 + if (!vms->legacy_smmuv3_present) {
1237 + acpi_dsdt_add_tegra241_cmdqv(scope, vms);
1238 + }
1239 +
1240 aml_append(dsdt, scope);
1241
1242 pci0_scope = aml_scope("\\_SB.PCI0");