hw/cxl: Add a performant (and correct) path for the non interleaved cases
The CXL address to device decoding logic is complex because of the need to correctly decode fine grained interleave. The current implementation prevents use with KVM where executed instructions may reside in that memory and gives very slow performance even in TCG. In many real cases non interleaved memory configurations are useful and for those we can use a more conventional memory region alias allowing similar performance to other memory in the system. Whether this fast path is applicable can be established once the full set of HDM decoders has been committed (in whatever order the guest decides to commit them). As such a check is performed on each commit/uncommit of HDM decoder to establish if the alias should be added or removed. Reviewed-by: Li Zhijian <lizhijian@fujitsu.com> Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Gregory Price <gourry@gourry.net> Tested-by: Gregory Price <gourry@gourry.net> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260318171918.146-4-alireza.sanaee@huawei.com>
Alireza Sanaee committed
Mar 18, 2026 at 17:19 UTC
680935c9a6fff2df0665b680322b9e9d0cdb692b
5 files changed
+216
hw/cxl/cxl-component-utils.c
+6
@@ -143,6 +143,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
143
value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
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}
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stl_le_p((uint8_t *)cache_mem + offset, value);
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+
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+ if (should_commit) {
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+ cfmws_update_non_interleaved(true);
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+ } else if (should_uncommit) {
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+ cfmws_update_non_interleaved(false);
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+ }
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}
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static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset,
hw/cxl/cxl-host.c
+201
@@ -264,6 +264,207 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr,
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return d;
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}
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+typedef struct CXLDirectPTState {
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+ CXLType3Dev *ct3d;
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+ hwaddr decoder_base;
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+ hwaddr decoder_size;
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+ hwaddr dpa_base;
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+ unsigned int hdm_decoder_idx;
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+} CXLDirectPTState;
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+
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+static void cxl_fmws_direct_passthrough_setup(CXLDirectPTState *state,
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+ CXLFixedWindow *fw)
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+{
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+ CXLType3Dev *ct3d = state->ct3d;
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+ MemoryRegion *mr = NULL;
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+ uint64_t vmr_size = 0, pmr_size = 0, offset = 0;
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+ MemoryRegion *direct_mr;
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+ g_autofree char *direct_mr_name;
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+ unsigned int idx = state->hdm_decoder_idx;
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+
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+ if (ct3d->hostvmem) {
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+ MemoryRegion *vmr = host_memory_backend_get_memory(ct3d->hostvmem);
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+
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+ vmr_size = memory_region_size(vmr);
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+ if (state->dpa_base < vmr_size) {
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+ mr = vmr;
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+ offset = state->dpa_base;
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+ }
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+ }
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+ if (!mr && ct3d->hostpmem) {
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+ MemoryRegion *pmr = host_memory_backend_get_memory(ct3d->hostpmem);
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+
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+ pmr_size = memory_region_size(pmr);
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+ if (state->dpa_base - vmr_size < pmr_size) {
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+ mr = pmr;
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+ offset = state->dpa_base - vmr_size;
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+ }
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+ }
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+ if (!mr) {
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+ return;
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+ }
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+
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+ if (ct3d->direct_mr_fw[idx]) {
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+ return;
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+ }
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+
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+ direct_mr = &ct3d->direct_mr[idx];
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+ direct_mr_name = g_strdup_printf("cxl-direct-mapping-alias-%u", idx);
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+ if (!direct_mr_name) {
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+ return;
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+ }
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+
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+ memory_region_init_alias(direct_mr, OBJECT(ct3d), direct_mr_name, mr,
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+ offset, state->decoder_size);
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+ memory_region_transaction_begin();
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+ memory_region_add_subregion(&fw->mr,
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+ state->decoder_base - fw->base, direct_mr);
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+ memory_region_transaction_commit();
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+ ct3d->direct_mr_fw[idx] = fw;
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+}
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+
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+static void cxl_fmws_direct_passthrough_remove(CXLType3Dev *ct3d,
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+ uint64_t decoder_base,
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+ unsigned int idx)
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+{
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+ CXLFixedWindow *owner_fw = ct3d->direct_mr_fw[idx];
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+ MemoryRegion *direct_mr = &ct3d->direct_mr[idx];
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+
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+ if (!owner_fw) {
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+ return;
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+ }
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+
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+ if (!memory_region_is_mapped(direct_mr)) {
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+ return;
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+ }
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+
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+ if (cxl_cfmws_find_device(owner_fw, decoder_base, false)) {
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+ return;
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+ }
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+
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+ memory_region_transaction_begin();
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+ memory_region_del_subregion(&owner_fw->mr, direct_mr);
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+ object_unparent(OBJECT(direct_mr));
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+ memory_region_transaction_commit();
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+ ct3d->direct_mr_fw[idx] = NULL;
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+}
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+
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+static int cxl_fmws_direct_passthrough(Object *obj, void *opaque)
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+{
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+ CXLDirectPTState *state = opaque;
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+ CXLFixedWindow *fw;
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+
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+ if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {
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+ return 0;
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+ }
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+
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+ fw = CXL_FMW(obj);
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+
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+ /* Verify not interleaved */
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+ if (!cxl_cfmws_find_device(fw, state->decoder_base, false)) {
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+ return 0;
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+ }
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+
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+ cxl_fmws_direct_passthrough_setup(state, fw);
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+
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+ return 0;
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+}
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+
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+static int update_non_interleaved(Object *obj, void *opaque)
374
+{
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+ const int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
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+ bool commit = *(bool *)opaque;
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+ CXLType3Dev *ct3d;
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+ uint32_t *cache_mem;
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+ unsigned int hdm_count, i;
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+ int interleave_ways_dec;
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+ uint32_t cap;
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+ uint64_t dpa_base = 0;
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+
384
+ if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {
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+ return 0;
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+ }
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+
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+ ct3d = CXL_TYPE3(obj);
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+ cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
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+ cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY);
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+ hdm_count = cxl_decoder_count_dec(FIELD_EX32(cap,
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+ CXL_HDM_DECODER_CAPABILITY,
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+ DECODER_COUNT));
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+ for (i = 0; i < hdm_count; i++) {
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+ uint64_t decoder_base, decoder_size, skip;
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+ uint32_t hdm_ctrl, low, high;
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+ int iw, committed;
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+
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+ hdm_ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc);
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+ committed = FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED);
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+
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+ /*
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+ * Optimization: Looking for a fully committed path; if the type 3 HDM
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+ * decoder is not commmitted, it cannot lie on such a path.
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+ */
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+ if (commit && !committed) {
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+ return 0;
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+ }
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+
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+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_LO +
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+ i * hdm_inc);
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+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_HI +
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+ i * hdm_inc);
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+ skip = ((uint64_t)high << 32) | (low & 0xf0000000);
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+ dpa_base += skip;
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+
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+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc);
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+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc);
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+ decoder_size = ((uint64_t)high << 32) | (low & 0xf0000000);
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+
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+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc);
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+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc);
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+ decoder_base = ((uint64_t)high << 32) | (low & 0xf0000000);
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+
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+ iw = FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, IW);
426
+
427
+ if (iw == 0) {
428
+ if (!commit) {
429
+ cxl_fmws_direct_passthrough_remove(ct3d, decoder_base, i);
430
+ } else {
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+ CXLDirectPTState state = {
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+ .ct3d = ct3d,
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+ .decoder_base = decoder_base,
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+ .decoder_size = decoder_size,
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+ .dpa_base = dpa_base,
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+ .hdm_decoder_idx = i,
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+ };
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+
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+ object_child_foreach_recursive(object_get_root(),
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+ cxl_fmws_direct_passthrough,
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+ &state);
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+ }
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+ }
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+
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+ interleave_ways_dec = cxl_interleave_ways_dec(iw, &error_fatal);
446
+ if (interleave_ways_dec == 0) {
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+ return 0;
448
+ }
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+
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+ dpa_base += decoder_size / interleave_ways_dec;
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+ }
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+
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+ return 0;
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+}
455
+
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+void cfmws_update_non_interleaved(bool commit)
457
+{
458
+ /*
459
+ * Walk endpoints to find both committed and uncommitted decoders,
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+ * then check if they are not interleaved (but the path is fully set up).
461
+ */
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+ object_child_foreach_recursive(object_get_root(),
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+ update_non_interleaved, &commit);
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+
465
+ return;
466
+}
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+
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static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
469
unsigned size, MemTxAttrs attrs)
470
{
hw/mem/cxl_type3.c
+4
@@ -427,6 +427,8 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
427
ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
428
429
stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl);
430
+
431
+ cfmws_update_non_interleaved(true);
432
}
433
434
static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which)
@@ -442,6 +444,8 @@ static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which)
444
ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
445
446
stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl);
447
+
448
+ cfmws_update_non_interleaved(false);
449
}
450
451
static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
include/hw/cxl/cxl.h
+1
@@ -71,4 +71,5 @@ CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp);
71
typedef struct CXLDownstreamPort CXLDownstreamPort;
72
DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP)
73
74
+void cfmws_update_non_interleaved(bool commit);
75
#endif
include/hw/cxl/cxl_device.h
+4
@@ -685,6 +685,8 @@ typedef struct CXLSetFeatureInfo {
685
size_t data_size;
686
} CXLSetFeatureInfo;
687
688
+typedef struct CXLFixedWindow CXLFixedWindow;
689
+
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struct CXLSanitizeInfo;
691
692
typedef struct CXLAlertConfig {
@@ -712,6 +714,8 @@ struct CXLType3Dev {
714
uint64_t sn;
715
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/* State */
717
+ MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT];
718
+ CXLFixedWindow *direct_mr_fw[CXL_HDM_DECODER_COUNT];
719
AddressSpace hostvmem_as;
720
AddressSpace hostpmem_as;
721
CXLComponentState cxl_cstate;