@samitouri / QOSamiQemu / commits / 6985cfc875

disas/riscv: Fix th.srri decoding

target/riscv/xthead.decode defines th.srri as funct6=000100 in bits 31:26, with the 6-bit immediate in bits 25:20. decode_xtheadbb() switches on bits 31:25, i.e. funct6 plus imm[5]. Therefore valid th.srri encodings are 0001000 and 0001001. The current 0000100 and 0000101 cases use the wrong funct6 value and decode valid th.srri instructions as illegal. Fix the cases to match funct6=000100 with both imm[5] values. Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions") Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703-b4-disas-xthead-fix-riscv-next-v4-1-84c566330bc7@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

TANG Tiancheng committed Jul 3, 2026 at 13:03 UTC 6985cfc87512e96c0abfa7fffc836e7bd3889048

1 file changed +4 -2

disas/riscv-xthead.c

+4 -2

@@ -315,8 +315,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)

315 op = rv_op_th_revw;

316 }

317 break;

318 - case 0b0000100:

319 - case 0b0000101: op = rv_op_th_srri; break;

318 + case 0b0001000:

319 + case 0b0001001:

320 + op = rv_op_th_srri;

321 + break;

322 }

323 break;

324 case 2: op = rv_op_th_ext; break;