hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users
Now that Aspeed2700SCUState has been introduced, update the AST1700 and AST27x0 SoCs to instantiate the AST2700-specific SCU subclass instead of the generic AspeedSCUState. Also update the AST27x0 FC board to link the SSP/TSP coprocessors to the AST2700 SCU instance. This prepares the AST2700 platform for subsequent patches that move AST2700-specific SCU functionality into the subclass. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260717084559.3477061-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Jul 17, 2026 at 08:46 UTC
69ba4d5b967cbc7995ac30775fdf4bc1e7350788
4 files changed
+12
-11
hw/arm/aspeed_ast27x0-fc.c
+2
-2
@@ -158,7 +158,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
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object_property_set_link(OBJECT(&s->ssp), "sram",
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OBJECT(&psp->sram), &error_abort);
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object_property_set_link(OBJECT(&s->ssp), "scu",
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- OBJECT(&psp->scu), &error_abort);
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+ OBJECT(&s->ca35.scu), &error_abort);
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if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
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return false;
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}
@@ -190,7 +190,7 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
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object_property_set_link(OBJECT(&s->tsp), "sram",
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OBJECT(&psp->sram), &error_abort);
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object_property_set_link(OBJECT(&s->tsp), "scu",
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- OBJECT(&psp->scu), &error_abort);
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+ OBJECT(&s->ca35.scu), &error_abort);
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if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
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return false;
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}
hw/arm/aspeed_ast27x0.c
+8
-8
@@ -435,12 +435,12 @@ static void aspeed_soc_ast2700_init(Object *obj)
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object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
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- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
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- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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+ object_initialize_child(obj, "scu", &a->scu, TYPE_ASPEED_2700_SCU);
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+ qdev_prop_set_uint32(DEVICE(&a->scu), "silicon-rev",
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sc->silicon_rev);
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- object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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+ object_property_add_alias(obj, "hw-strap1", OBJECT(&a->scu),
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"hw-strap1");
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- object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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+ object_property_add_alias(obj, "hw-prot-key", OBJECT(&a->scu),
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"hw-prot-key");
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object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
@@ -808,10 +808,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
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sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
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/* SCU */
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- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->scu), errp)) {
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return;
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}
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- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
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+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->scu), 0,
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sc->memmap[ASPEED_DEV_SCU]);
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/* SCU1 */
@@ -934,7 +934,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
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AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
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hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
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- object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
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+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&a->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
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return;
@@ -1037,7 +1037,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
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aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC));
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/* Timer */
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- object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
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+ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&a->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
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return;
include/hw/arm/aspeed_ast1700.h
+1
-1
@@ -41,7 +41,7 @@ struct AspeedAST1700SoCState {
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MemoryRegion sram;
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AspeedSMCState spi;
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AspeedADCState adc;
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- AspeedSCUState scu;
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+ Aspeed2700SCUState scu;
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AspeedGPIOState gpio;
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AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM];
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AspeedI2CState i2c;
include/hw/arm/aspeed_soc.h
+1
@@ -151,6 +151,7 @@ struct Aspeed27x0SoCState {
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AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
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GICv3State gic;
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MemoryRegion dram_empty;
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+ Aspeed2700SCUState scu;
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};
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#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"