target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
6ad626ee86ddac79385b1422edf212b9971bf4aa
4 files changed
+31
target/arm/tcg/fp8_helper.c
+16
@@ -168,6 +168,22 @@ void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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fp8_cvt_finish(env, &ctx);
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}
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+void HELPER(sve2_fcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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+{
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+ FP8Context ctx = fp8_src_start(env, desc, 0xf);
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+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];
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+ uint8_t *n = vn;
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+ uint16_t *d = vd;
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+ size_t nelem = simd_oprsz(desc) / 2;
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+
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+ for (size_t i = 0; i < nelem; ++i) {
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+ d[H2(i)] = fcvt_fp8_to_f16(n[H1(2 * i + ctx.high)],
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+ input_fmt, ctx.scale, &ctx.stat);
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+}
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+
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void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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{
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FP8Context ctx = fp8_src_start(env, desc, 0x3f);
target/arm/tcg/helper-fp8-defs.h
+1
@@ -9,3 +9,4 @@ DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_4(sve2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
target/arm/tcg/sve.decode
+5
@@ -1091,6 +1091,11 @@ FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn
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FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
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FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
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+F1CVT 01100101 00 001 000 001100 ..... ..... @rd_rn_e0
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+F2CVT 01100101 00 001 000 001101 ..... ..... @rd_rn_e0
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+F1CVTLT 01100101 00 001 001 001100 ..... ..... @rd_rn_e0
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+F2CVTLT 01100101 00 001 001 001101 ..... ..... @rd_rn_e0
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+
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BF1CVT 01100101 00 001 000 001110 ..... ..... @rd_rn_e0
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BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0
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BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0
target/arm/tcg/translate-sve.c
+9
@@ -4082,6 +4082,15 @@ static bool do_f8cvt(DisasContext *s, arg_rr_esz *a,
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return true;
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}
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+TRANS_FEAT_STREAMING_IF(F1CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
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+ do_f8cvt, a, gen_helper_sve2_fcvt_hb, false, false)
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+TRANS_FEAT_STREAMING_IF(F2CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
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+ do_f8cvt, a, gen_helper_sve2_fcvt_hb, true, false)
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+TRANS_FEAT_STREAMING_IF(F1CVTLT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
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+ do_f8cvt, a, gen_helper_sve2_fcvt_hb, false, true)
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+TRANS_FEAT_STREAMING_IF(F2CVTLT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
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+ do_f8cvt, a, gen_helper_sve2_fcvt_hb, true, true)
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+
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TRANS_FEAT_STREAMING_IF(BF1CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
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do_f8cvt, a, gen_helper_sve2_bfcvt, false, false)
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TRANS_FEAT_STREAMING_IF(BF2CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,