target/riscv: Fix size of ssp
As ssp holds a pointer, fix to 64 bits in size and make sure stores from TCG use the correct size to avoid problems on big endian hosts. Note, the cpu/ssp VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-10-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
6ba16ebfaccc89b36a748bffd4da2d4111c5326a
3 files changed
+17
-9
target/riscv/cpu.h
+1
-1
@@ -257,7 +257,7 @@ struct CPUArchState {
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/* elp state for zicfilp extension */
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bool elp;
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/* shadow stack register for zicfiss extension */
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- target_ulong ssp;
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+ uint64_t ssp;
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/* env place holder for extra word 2 during unwind */
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target_ulong excp_uw2;
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/* sw check code for sw check exception */
target/riscv/insn_trans/trans_rvzicfiss.c.inc
+13
-5
@@ -32,7 +32,9 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
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TCGLabel *skip = gen_new_label();
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uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
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TCGv data = tcg_temp_new();
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- tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ TCGv_i64 wide_addr = tcg_temp_new_i64();
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+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_trunc_i64_tl(addr, wide_addr);
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decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
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tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx),
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mxl_memop(ctx) | MO_ALIGN);
@@ -45,7 +47,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
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tcg_constant_i32(RISCV_EXCP_SW_CHECK));
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gen_set_label(skip);
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tcg_gen_addi_tl(addr, addr, tmp);
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- tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_ext_tl_i64(wide_addr, addr);
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+ tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
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return true;
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}
@@ -59,12 +62,15 @@ static bool trans_sspush(DisasContext *ctx, arg_sspush *a)
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TCGv addr = tcg_temp_new();
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int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
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TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
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+ TCGv_i64 wide_addr = tcg_temp_new_i64();
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decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
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- tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_trunc_i64_tl(addr, wide_addr);
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tcg_gen_addi_tl(addr, addr, tmp);
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tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx),
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mxl_memop(ctx) | MO_ALIGN);
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- tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_ext_tl_i64(wide_addr, addr);
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+ tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
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return true;
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}
@@ -76,7 +82,9 @@ static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
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}
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TCGv dest = dest_gpr(ctx, a->rd);
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- tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp));
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+ TCGv_i64 wide_addr = tcg_temp_new_i64();
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+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
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+ tcg_gen_trunc_i64_tl(dest, wide_addr);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
target/riscv/machine.c
+3
-3
@@ -391,11 +391,11 @@ static bool ssp_needed(void *opaque)
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static const VMStateDescription vmstate_ssp = {
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.name = "cpu/ssp",
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- .version_id = 1,
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- .minimum_version_id = 1,
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+ .version_id = 2,
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+ .minimum_version_id = 2,
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.needed = ssp_needed,
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.fields = (const VMStateField[]) {
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- VMSTATE_UINTTL(env.ssp, RISCVCPU),
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+ VMSTATE_UINT64(env.ssp, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};