@samitouri / QOSamiQemu / commits / 6bf66f0b5a

target/riscv: tidy up riscv_sysemu_ops

monitor_get_register at this moment has a TCG exclusive implementation for RISC-V, even though the callback is supposed to be arch independent. Until we address how KVM is going to implement it we need to filter it out in cpu.c. Same goes for get_phys_addr_debug - it has a TCG only implementation and KVM can't use it for now. It would also need to be filtered out, but since we're at it, let's convert it to the newer 'translate_for_debug' API too. Same restrictions apply. Suggested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260703180538.3346781-8-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jul 3, 2026 at 15:05 UTC 6bf66f0b5a4241af590dc7e2624852ef6dcc7704

4 files changed +18 -7

target/riscv/cpu.c

+4 -2

@@ -2693,11 +2693,13 @@ static int64_t riscv_get_arch_id(CPUState *cs)

2693

2694 static const struct SysemuCPUOps riscv_sysemu_ops = {

2695 .has_work = riscv_cpu_has_work,

2696 - .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,

2696 .write_elf64_note = riscv_cpu_write_elf64_note,

2697 .write_elf32_note = riscv_cpu_write_elf32_note,

2699 - .monitor_get_register = riscv_monitor_get_register_legacy,

2698 .legacy_vmsd = &vmstate_riscv_cpu,

2699 +#ifdef CONFIG_TCG

2700 + .translate_for_debug = riscv_cpu_translate_for_debug,

2701 + .monitor_get_register = riscv_monitor_get_register_legacy,

2702 +#endif

2703 };

2704 #endif

2705

target/riscv/cpu.h

+2 -1

@@ -665,7 +665,8 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,

665 MMUAccessType access_type,

666 int mmu_idx, MemTxAttrs attrs,

667 MemTxResult response, uintptr_t retaddr);

668 -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

668 +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr,

669 + TranslateForDebugResult *result);

670 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);

671 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);

672 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);

target/riscv/monitor.c

@@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)

245 mem_info_svxx(mon, env);

246 }

247

248 +#ifdef CONFIG_TCG

249 static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,

250 target_ulong *val, bool is_gprh)

251 {

@@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,

380

381 return -EINVAL;

382 }

383 +#endif

target/riscv/tcg/cpu_helper.c

+10 -4

@@ -1779,7 +1779,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,

1779 env->two_stage_indirect_lookup = two_stage_indirect;

1780 }

1781

1782 -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

1782 +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr,

1783 + TranslateForDebugResult *result)

1784 {

1785 RISCVCPU *cpu = RISCV_CPU(cs);

1786 CPURISCVState *env = &cpu->env;

@@ -1789,17 +1790,22 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

1790

1791 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,

1792 true, env->virt_enabled, true, false)) {

1792 - return -1;

1793 + return false;

1794 }

1795

1796 if (env->virt_enabled) {

1797 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,

1798 0, MMUIdx_U, false, true, true, false)) {

1798 - return -1;

1799 + return false;

1800 }

1801 }

1802

1802 - return phys_addr;

1803 + *result = (TranslateForDebugResult) {

1804 + .physaddr = phys_addr,

1805 + .lg_page_size = TARGET_PAGE_BITS,

1806 + .attrs.debug = 1,

1807 + };

1808 + return true;

1809 }

1810

1811 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,