disas/riscv: Handle aliases of csrrs during decode
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-24-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
6bfb6410562592a7f6a1e496c99600a58b838231
2 files changed
+17
-75
disas/riscv.c
+17
-68
@@ -1063,24 +1063,6 @@ static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
1063
rvc_end };
1064
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
1065
rvc_end };
1066
-static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
1067
- rvc_end };
1068
-static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
1069
- rvc_end };
1070
-static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
1071
- rvc_csr_eq_0xc02, rvc_end };
1072
-static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
1073
- rvc_csr_eq_0xc80, rvc_end };
1074
-static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
1075
- rvc_end };
1076
-static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
1077
- rvc_csr_eq_0xc82, rvc_end };
1078
-static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
1079
- rvc_end };
1080
-static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
1081
- rvc_end };
1082
-static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
1083
- rvc_end };
1066
static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
1067
static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1068
@@ -1163,19 +1145,6 @@ static const rv_comp_data rvcp_subw[] = {
1145
{ rv_op_illegal, NULL }
1146
};
1147
1166
-static const rv_comp_data rvcp_csrrs[] = {
1167
- { rv_op_rdcycle, rvcc_rdcycle },
1168
- { rv_op_rdtime, rvcc_rdtime },
1169
- { rv_op_rdinstret, rvcc_rdinstret },
1170
- { rv_op_rdcycleh, rvcc_rdcycleh },
1171
- { rv_op_rdtimeh, rvcc_rdtimeh },
1172
- { rv_op_rdinstreth, rvcc_rdinstreth },
1173
- { rv_op_frcsr, rvcc_frcsr },
1174
- { rv_op_frrm, rvcc_frrm },
1175
- { rv_op_frflags, rvcc_frflags },
1176
- { rv_op_illegal, NULL }
1177
-};
1178
-
1148
static const rv_comp_data rvcp_csrrwi[] = {
1149
{ rv_op_fsrmi, rvcc_fsrmi },
1150
{ rv_op_fsflagsi, rvcc_fsflagsi },
@@ -1751,7 +1720,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
1720
{ "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
1721
{ "wfi", rv_codec_none, rv_fmt_none },
1722
{ "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
1754
- { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
1723
+ { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
1724
{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
1725
{ "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
1726
{ "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
@@ -4440,7 +4409,22 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
4409
default: op = rv_op_csrrw; break;
4410
}
4411
break;
4443
- case 2: op = rv_op_csrrs; break;
4412
+ case 2:
4413
+ op = rv_op_csrrs;
4414
+ if (operand_rs1(inst) == 0) {
4415
+ switch (operand_csr12(inst)) {
4416
+ case 0x001: op = rv_op_frflags; break;
4417
+ case 0x002: op = rv_op_frrm; break;
4418
+ case 0x003: op = rv_op_frcsr; break;
4419
+ case 0xc00: op = rv_op_rdcycle; break;
4420
+ case 0xc01: op = rv_op_rdtime; break;
4421
+ case 0xc02: op = rv_op_rdinstret; break;
4422
+ case 0xc80: op = rv_op_rdcycleh; break;
4423
+ case 0xc81: op = rv_op_rdtimeh; break;
4424
+ case 0xc82: op = rv_op_rdinstreth; break;
4425
+ }
4426
+ }
4427
+ break;
4428
case 3: op = rv_op_csrrc; break;
4429
case 4:
4430
if (dec->cfg && dec->cfg->ext_zimop) {
@@ -5017,41 +5001,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
5001
return false;
5002
}
5003
break;
5020
- case rvc_csr_eq_0x003:
5021
- if (!(imm == 0x003)) {
5022
- return false;
5023
- }
5024
- break;
5025
- case rvc_csr_eq_0xc00:
5026
- if (!(imm == 0xc00)) {
5027
- return false;
5028
- }
5029
- break;
5030
- case rvc_csr_eq_0xc01:
5031
- if (!(imm == 0xc01)) {
5032
- return false;
5033
- }
5034
- break;
5035
- case rvc_csr_eq_0xc02:
5036
- if (!(imm == 0xc02)) {
5037
- return false;
5038
- }
5039
- break;
5040
- case rvc_csr_eq_0xc80:
5041
- if (!(imm == 0xc80)) {
5042
- return false;
5043
- }
5044
- break;
5045
- case rvc_csr_eq_0xc81:
5046
- if (!(imm == 0xc81)) {
5047
- return false;
5048
- }
5049
- break;
5050
- case rvc_csr_eq_0xc82:
5051
- if (!(imm == 0xc82)) {
5052
- return false;
5053
- }
5054
- break;
5004
default: break;
5005
}
5006
c++;
disas/riscv.h
-7
@@ -86,13 +86,6 @@ typedef enum {
86
rvc_imm_eq_p1,
87
rvc_csr_eq_0x001,
88
rvc_csr_eq_0x002,
89
- rvc_csr_eq_0x003,
90
- rvc_csr_eq_0xc00,
91
- rvc_csr_eq_0xc01,
92
- rvc_csr_eq_0xc02,
93
- rvc_csr_eq_0xc80,
94
- rvc_csr_eq_0xc81,
95
- rvc_csr_eq_0xc82,
89
} rvc_constraint;
90
91
typedef enum {