hw/riscv/riscv-iommu: forbid GATE/SADE if caps.AMO_HWADD is zero
When capabilities.AMO_HWADD isn't set, DC.tc.GADE and DC.tc.SADE are reserved bits and setting them throws a DDT_MISCONFIGURED error. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3549 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <20260630172110.1866951-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jun 30, 2026 at 14:21 UTC
6d2b9d542fe2cec17eec71bdb33e45bee8805105
2 files changed
+6
hw/riscv/riscv-iommu-bits.h
+1
@@ -86,6 +86,7 @@ struct riscv_iommu_pq_record {
86
#define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19)
87
#define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22)
88
#define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23)
89
+#define RISCV_IOMMU_CAP_AMO_HWAD BIT_ULL(24)
90
#define RISCV_IOMMU_CAP_ATS BIT_ULL(25)
91
#define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26)
92
#define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28)
hw/riscv/riscv-iommu.c
+5
@@ -417,6 +417,11 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
417
const bool ade =
418
ctx->tc & (pass ? RISCV_IOMMU_DC_TC_GADE : RISCV_IOMMU_DC_TC_SADE);
419
420
+ if (ade && !(s->cap & RISCV_IOMMU_CAP_AMO_HWAD)) {
421
+ /* GADE/SADE are reserved bits if AMO_HWAD is cleared. */
422
+ return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED;
423
+ }
424
+
425
/* Address range check before first level lookup */
426
if (!sc[pass].step) {
427
const uint64_t va_len = va_skip + va_bits;