target/ppc: Move fixed-point byte-reversal store insns to decodetree
Move the below PPC instructions to decodetree specification: st{d,h,w}brx, st{d,w,h,b}cix : X-form The changes were verified by validating that the TCG micro-ops generated by those insns remain the same. These TCG micro-ops were captured with the `-d op,in_asm` QEMU flag. Additionally, remove GEN_STX and GEN_STX_E macros as they are no longer used anywhere else. Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-12-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Amit Machhiwal committed
Aug 27, 2026 at 18:59 UTC
6e9536dbdb0387a04d9f78bf99ce1b52c148ff75
3 files changed
+95
-44
target/ppc/insn32.decode
+8
@@ -372,6 +372,14 @@ STVDX 011111 ..... ..... ..... 0010010001 - @X
372
STSKU 111110 ..... ..... ............. 0 11 @DD
373
STCXU 111110 ..... ..... ............. 1 11 @DD
374
375
+STDBRX 011111 ..... ..... ..... 1010010100 - @X
376
+STDCIX 011111 ..... ..... ..... 1111110101 - @X
377
+STWCIX 011111 ..... ..... ..... 1110010101 - @X
378
+STHCIX 011111 ..... ..... ..... 1110110101 - @X
379
+STBCIX 011111 ..... ..... ..... 1111010101 - @X
380
+STHBRX 011111 ..... ..... ..... 1110010110 - @X
381
+STWBRX 011111 ..... ..... ..... 1010010110 - @X
382
+
383
### Fixed-Point Compare Instructions
384
385
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
target/ppc/translate.c
+8
-44
@@ -2529,23 +2529,6 @@ GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2529
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2530
#endif
2531
2532
-/*** Integer store ***/
2533
-#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2534
-static void glue(gen_, name##x)(DisasContext *ctx) \
2535
-{ \
2536
- TCGv EA; \
2537
- chk(ctx); \
2538
- gen_set_access_type(ctx, ACCESS_INT); \
2539
- EA = tcg_temp_new(); \
2540
- gen_addr_reg_index(ctx, EA); \
2541
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2542
-}
2543
-#define GEN_STX(name, stop, opc2, opc3, type) \
2544
- GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2545
-
2546
-#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2547
- GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2548
-
2532
#define GEN_STEPX(name, stop, opc2, opc3) \
2533
static void glue(gen_, name##epx)(DisasContext *ctx) \
2534
{ \
@@ -2565,12 +2548,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2548
GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)
2549
#endif
2550
2568
-#if defined(TARGET_PPC64)
2569
-GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2570
-GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2571
-GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2572
-GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2573
-#endif
2551
/*** Integer load and store with byte reverse ***/
2552
2553
/* lhbrx */
@@ -2582,15 +2559,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2559
#if defined(TARGET_PPC64)
2560
/* ldbrx */
2561
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2585
-/* stdbrx */
2586
-GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2562
#endif /* TARGET_PPC64 */
2563
2589
-/* sthbrx */
2590
-GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2591
-/* stwbrx */
2592
-GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2593
-
2564
/*** Integer load and store multiple ***/
2565
2566
/* lmw */
@@ -5147,9 +5117,17 @@ static int64_t dw_compose_ea(DisasContext *ctx, int x)
5117
return true; \
5118
} \
5119
} while (0)
5120
+#define REQUIRE_HVRM(CTX) \
5121
+ do { \
5122
+ if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
5123
+ gen_priv_opc(CTX); \
5124
+ return true; \
5125
+ } \
5126
+ } while (0)
5127
#else
5128
#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
5129
#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
5130
+#define REQUIRE_HVRM(CTX) do { gen_priv_opc(CTX); return true; } while (0)
5131
#endif
5132
5133
/*
@@ -5756,20 +5734,6 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
5734
GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
5735
#endif
5736
5759
-#undef GEN_STX_E
5760
-#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
5761
-GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
5762
-
5763
-#if defined(TARGET_PPC64)
5764
-GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
5765
-GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
5766
-GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
5767
-GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
5768
-GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
5769
-#endif
5770
-GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
5771
-GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
5772
-
5737
#undef GEN_STEPX
5738
#define GEN_STEPX(name, ldop, opc2, opc3) \
5739
GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
target/ppc/translate/fixedpoint-impl.c.inc
+79
@@ -566,6 +566,85 @@ TRANS(ADDIC_, do_add_D, false, true, false, true);
566
TRANS(SLD, do_shift_X_rc, tcg_gen_shl_tl);
567
TRANS(SRD, do_shift_X_rc, tcg_gen_shr_tl);
568
569
+static bool do_stxx(DisasContext *ctx, arg_X *a,
570
+ void(*op)(DisasContext *, TCGv, TCGv), bool is_hvrm)
571
+{
572
+ TCGv ea;
573
+
574
+ if (is_hvrm) {
575
+ REQUIRE_HVRM(ctx);
576
+ }
577
+
578
+ gen_set_access_type(ctx, ACCESS_INT);
579
+ ea = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
580
+ op(ctx, cpu_gpr[a->rt], ea);
581
+
582
+ return true;
583
+}
584
+
585
+TRANS(STHBRX, do_stxx, gen_qemu_st16r, 0);
586
+TRANS(STWBRX, do_stxx, gen_qemu_st32r, 0);
587
+
588
+static bool trans_STDBRX(DisasContext *ctx, arg_STDBRX *a)
589
+{
590
+ REQUIRE_64BIT(ctx);
591
+ REQUIRE_INSNS_FLAGS2(ctx, DBRX);
592
+#if defined(TARGET_PPC64)
593
+ return do_stxx(ctx, a, gen_qemu_st64r_i64, false);
594
+#else
595
+ qemu_build_not_reached();
596
+#endif
597
+ return true;
598
+}
599
+
600
+static bool trans_STDCIX(DisasContext *ctx, arg_STDCIX *a)
601
+{
602
+ REQUIRE_64BIT(ctx);
603
+ REQUIRE_INSNS_FLAGS(ctx, CILDST);
604
+#if defined(TARGET_PPC64)
605
+ return do_stxx(ctx, a, gen_qemu_st64_i64, true);
606
+#else
607
+ qemu_build_not_reached();
608
+#endif
609
+ return true;
610
+}
611
+
612
+static bool trans_STWCIX(DisasContext *ctx, arg_STWCIX *a)
613
+{
614
+ REQUIRE_64BIT(ctx);
615
+ REQUIRE_INSNS_FLAGS(ctx, CILDST);
616
+#if defined(TARGET_PPC64)
617
+ return do_stxx(ctx, a, gen_qemu_st32, true);
618
+#else
619
+ qemu_build_not_reached();
620
+#endif
621
+ return true;
622
+}
623
+
624
+static bool trans_STHCIX(DisasContext *ctx, arg_STHCIX *a)
625
+{
626
+ REQUIRE_64BIT(ctx);
627
+ REQUIRE_INSNS_FLAGS(ctx, CILDST);
628
+#if defined(TARGET_PPC64)
629
+ return do_stxx(ctx, a, gen_qemu_st16, true);
630
+#else
631
+ qemu_build_not_reached();
632
+#endif
633
+ return true;
634
+}
635
+
636
+static bool trans_STBCIX(DisasContext *ctx, arg_STBCIX *a)
637
+{
638
+ REQUIRE_64BIT(ctx);
639
+ REQUIRE_INSNS_FLAGS(ctx, CILDST);
640
+#if defined(TARGET_PPC64)
641
+ return do_stxx(ctx, a, gen_qemu_st8, true);
642
+#else
643
+ qemu_build_not_reached();
644
+#endif
645
+ return true;
646
+}
647
+
648
static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
649
{
650
gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],