target/arm: Implement FRINT{32,64}{X,Z}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
6ebbd57c3652776c46679fe4f75776a19ee71a6b
4 files changed
+70
target/arm/tcg/helper-sve-defs.h
+9
@@ -1441,6 +1441,15 @@ DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
1441
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sve2p2_frint32_s, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sve2p2_frint64_s, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sve2p2_frint32_d, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sve2p2_frint64_d, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, fpst, i32)
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+
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DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG,
target/arm/tcg/sve.decode
+20
@@ -1259,6 +1259,26 @@ FRINTA_z 01100100 .. 011 001 100 ... ..... ..... @rd_pg_rn
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FRINTX_z 01100100 .. 011 001 110 ... ..... ..... @rd_pg_rn
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FRINTI_z 01100100 .. 011 001 111 ... ..... ..... @rd_pg_rn
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+FRINT32X_s_m 01100101 00 010 001 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT32X_d_m 01100101 00 010 011 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT64X_s_m 01100101 00 010 101 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT64X_d_m 01100101 00 010 111 101 ... ..... ..... @rd_pg_rn_e0
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+
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+FRINT32X_s_z 01100100 00 011 100 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT32X_d_z 01100100 00 011 100 111 ... ..... ..... @rd_pg_rn_e0
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+FRINT64X_s_z 01100100 00 011 101 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT64X_d_z 01100100 00 011 101 111 ... ..... ..... @rd_pg_rn_e0
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+
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+FRINT32Z_s_m 01100101 00 010 000 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT32Z_d_m 01100101 00 010 010 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT64Z_s_m 01100101 00 010 100 101 ... ..... ..... @rd_pg_rn_e0
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+FRINT64Z_d_m 01100101 00 010 110 101 ... ..... ..... @rd_pg_rn_e0
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+
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+FRINT32Z_s_z 01100100 00 011 100 100 ... ..... ..... @rd_pg_rn_e0
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+FRINT32Z_d_z 01100100 00 011 100 110 ... ..... ..... @rd_pg_rn_e0
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+FRINT64Z_s_z 01100100 00 011 101 100 ... ..... ..... @rd_pg_rn_e0
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+FRINT64Z_d_z 01100100 00 011 101 110 ... ..... ..... @rd_pg_rn_e0
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+
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# SVE floating-point unary operations
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FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
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FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
target/arm/tcg/sve_helper.c
+5
@@ -5017,6 +5017,11 @@ DO_ZPZ_FP(sve_frintx_h, uint16_t, H1_2, float16_round_to_int)
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DO_ZPZ_FP(sve_frintx_s, uint32_t, H1_4, float32_round_to_int)
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DO_ZPZ_FP(sve_frintx_d, uint64_t, H1_8, float64_round_to_int)
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+DO_ZPZ_FP(sve2p2_frint32_s, uint32_t, H1_4, helper_frint32_s)
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+DO_ZPZ_FP(sve2p2_frint64_s, uint32_t, H1_4, helper_frint64_s)
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+DO_ZPZ_FP(sve2p2_frint32_d, uint64_t, H1_8, helper_frint32_d)
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+DO_ZPZ_FP(sve2p2_frint64_d, uint64_t, H1_8, helper_frint64_d)
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+
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DO_ZPZ_FP(sve_frecpx_h, uint16_t, H1_2, helper_frecpx_f16)
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DO_ZPZ_FP(sve_frecpx_s, uint32_t, H1_4, helper_frecpx_f32)
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DO_ZPZ_FP(sve_frecpx_d, uint64_t, H1_8, helper_frecpx_f64)
target/arm/tcg/translate-sve.c
+36
@@ -4730,6 +4730,42 @@ TRANS_FEAT(FRINTZ_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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TRANS_FEAT(FRINTA_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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FPROUNDING_TIEAWAY, 1, frint_fns[a->esz])
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+TRANS_FEAT(FRINT32X_s_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint32_s, a, 0, FPST_A64)
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+TRANS_FEAT(FRINT32X_d_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint32_d, a, 0, FPST_A64)
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+TRANS_FEAT(FRINT64X_s_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint64_s, a, 0, FPST_A64)
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+TRANS_FEAT(FRINT64X_d_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint64_d, a, 0, FPST_A64)
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+
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+TRANS_FEAT(FRINT32X_s_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint32_s, a, 1, FPST_A64)
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+TRANS_FEAT(FRINT32X_d_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint32_d, a, 1, FPST_A64)
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+TRANS_FEAT(FRINT64X_s_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint64_s, a, 1, FPST_A64)
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+TRANS_FEAT(FRINT64X_d_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve2p2_frint64_d, a, 1, FPST_A64)
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+
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+TRANS_FEAT(FRINT32Z_s_m, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint32_s)
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+TRANS_FEAT(FRINT32Z_d_m, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint32_d)
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+TRANS_FEAT(FRINT64Z_s_m, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint64_s)
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+TRANS_FEAT(FRINT64Z_d_m, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint64_d)
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+
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+TRANS_FEAT(FRINT32Z_s_z, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint32_s)
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+TRANS_FEAT(FRINT32Z_d_z, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint32_d)
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+TRANS_FEAT(FRINT64Z_s_z, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint64_s)
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+TRANS_FEAT(FRINT64Z_d_z, aa64_sme2p2_or_sve2p2, do_frint_mode,
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+ a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint64_d)
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+
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static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
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NULL, gen_helper_sve_frecpx_h,
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gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,