tests/functional/hexagon: enable more arch_tests cases
Add more tests from hexagon-arch-tests, enabled by QTimer device. These exercise cache maintenance ops, l2vic, thread start/stop, tlb/mmu operations, and user-mode transitions. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260806042723.3785369-19-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 5, 2026 at 21:27 UTC
701eb2ac98ba543a3a458a7fcaf8cc0f5e469ed4
1 file changed
+32
tests/functional/hexagon/test_arch_tests.py
+32
@@ -58,6 +58,38 @@ class ArchTestsUart(QemuSystemTest):
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"""
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self.run_uart_test("test_int_steering")
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+ def test_cache(self) -> None:
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+ """Tests cache operations: dckill/ickill, l2kill, dczeroa,
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+ dccleaninva, cache disable/enable, barriers, and dcinva/dccleana.
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+ """
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+ self.run_uart_test("test_cache")
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+
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+ def test_l2vic(self) -> None:
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+ """Tests the L2VIC interrupt controller: enable readback,
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+ interrupt type readback, VID capture, and the fast interface.
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+ """
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+ self.run_uart_test("test_l2vic")
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+
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+ def test_threads(self) -> None:
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+ """Tests hardware thread management: start/stop, MODECTL state,
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+ per-thread HTID, shared memory, wait/resume, STID priority, and
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+ SCHEDCFG/BESTWAIT readback.
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+ """
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+ self.run_uart_test("test_threads")
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+
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+ def test_tlb_mmu(self) -> None:
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+ """Tests TLB/MMU operations: write/read/probe/invalidate,
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+ global entries, multiple entries, overwrite, ASID matching,
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+ and permission checks.
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+ """
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+ self.run_uart_test("test_tlb_mmu")
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+
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+ def test_user_mode(self) -> None:
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+ """Tests user mode / privilege transitions: supervisor mode,
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+ SSR UM/IE/XE/CE/PE bits, and the trap0 user-mode exit handler.
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+ """
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+ self.run_uart_test("test_user_mode")
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+
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if __name__ == "__main__":
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QemuSystemTest.main()