target/arm: Fix b16b16 feature test for SME2 BFCLAMP, BFMAX, BFMIN
These are controlled by FEAT_SVE_B16B16 not FEAT_SME_B16B16. Cc: qemu-stable@nongnu.org Fixes: bc65d2bd1cb ("target/arm: Implement SME2 Multiple and Single SVE Destructive") Fixes: 930760eb753 ("target/arm: Implement SME2 Multiple Vectors SVE Destructive") Fixes: 8b61eff8e72 ("target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jul 31, 2026 at 11:24 UTC
702252a0dbc3ad9a51e4092a986b2f98e8c6adcb
1 file changed
+3
-3
target/arm/tcg/translate-sme.c
+3
-3
@@ -756,7 +756,7 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,
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return false;
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}
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/* These insns use MO_8 to encode BFloat16. */
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- if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
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+ if (esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
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return false;
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}
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if (!sme_sm_enabled_check(s)) {
@@ -793,7 +793,7 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,
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if (fn == NULL) {
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return false;
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}
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- if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
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+ if (esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
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return false;
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}
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if (!sme_sm_enabled_check(s)) {
@@ -1850,7 +1850,7 @@ static bool trans_FCLAMP(DisasContext *s, arg_zzz_en *a)
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return false;
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}
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/* This insn uses MO_8 to encode BFloat16. */
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- if (a->esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
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+ if (a->esz == MO_8 && !dc_isar_feature(aa64_sve_b16b16, s)) {
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return false;
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}
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if (!sme_sm_enabled_check(s)) {