disas/riscv: Do not recognize c.{addw, subw} with rv32
These code points are reserved with RV32. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-19-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
70c0e443432dda01d4e603961e0baee54e668f4d
1 file changed
+10
-2
disas/riscv.c
+10
-2
@@ -3060,8 +3060,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
3060
case 1: op = rv_op_c_xor; break;
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case 2: op = rv_op_c_or; break;
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case 3: op = rv_op_c_and; break;
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- case 4: op = rv_op_c_subw; break;
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- case 5: op = rv_op_c_addw; break;
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+ case 4:
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+ if (isa != rv32) {
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+ op = rv_op_c_subw;
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+ }
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+ break;
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+ case 5:
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+ if (isa != rv32) {
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+ op = rv_op_c_addw;
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+ }
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+ break;
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case 6: op = rv_op_c_mul; break;
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case 7:
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switch ((inst >> 2) & 0b111) {