@samitouri / QOSamiQemu / commits / 70f062675a

s390x/diag: Implement DIAG 320 subcode 2

DIAG 320 subcode 2 provides verification-certificates (VCs) that are in the certificate store. Only X509 certificates in DER format and SHA-256 hash type are recognized. The subcode value is denoted by setting the second-left-most bit of an 8-byte field. The Verification Certificate Block (VCB) contains the output data when the operation completes successfully. It includes a common header followed by zero or more Verification Certificate Entries (VCEs), depending on the VCB input length and the VC range (from the first VC index to the last VC index) in the certificate store. Each VCE contains information about a certificate retrieved from the S390IPLCertificateStore, such as the certificate name, key type, key ID length, hash length, and the raw certificate data. The key ID and hash are extracted from the raw certificate by the crypto API. Note: SHA2-256 VC hash type is required for retrieving the hash (fingerprint) of the certificate. Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Reviewed-by: Collin Walling <walling@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-10-zycai@linux.ibm.com Signed-off-by: Eric Farman <farman@linux.ibm.com>

Zhuoying Cai committed Jul 30, 2026 at 17:45 UTC 70f062675acbf0932b2177c062fed66a316ca2f8
3 files changed +377 -1
docs/specs/s390x-secure-ipl.rst
+24
@@ -42,3 +42,27 @@ Subcode 1 - query verification certificate storage information
42 The output is returned in the verification-certificate-storage-size block
43 (VCSSB). A VCSSB length of 4 indicates that no certificates are available
44 in the CS.
45 +
46 +Subcode 2 - store verification certificates
47 + Provides VCs that are in the certificate store.
48 +
49 + The output is provided in a VCB, which includes a common header followed by
50 + zero or more verification-certificate entries (VCEs).
51 +
52 + The instruction expects the cert store to maintain an origin of 1 for the
53 + index (i.e. a retrieval of the first certificate in the store should be
54 + denoted by setting first-VC to 1).
55 +
56 + The first-VC and last-VC fields of the VCB specify the index range of
57 + VCs to be stored in the VCB. Certs are stored sequentially, starting
58 + with first-VC index. As each cert is stored, a "stored count" is
59 + incremented. If there is not enough space to store all certs requested
60 + by the index range, a "remaining count" will be recorded and no more
61 + certificates will be stored.
62 +
63 + Each VCE contains a header followed by information extracted from a
64 + certificate within the certificate store. The information includes:
65 + key-id, hash, and certificate data. This information is stored
66 + contiguously in a VCE (with zero-padding). Following the header, the
67 + key-id is immediately stored. The hash and certificate data follow and
68 + may be accessed via the respective offset fields stored in the VCE.
include/hw/s390x/ipl/diag320.h
+38
@@ -12,19 +12,45 @@
12
13 #define DIAG_320_SUBC_QUERY_ISM 0
14 #define DIAG_320_SUBC_QUERY_VCSI 1
15 +#define DIAG_320_SUBC_STORE_VC 2
16
17 #define DIAG_320_RC_OK 0x0001
18 #define DIAG_320_RC_NOT_SUPPORTED 0x0102
19 #define DIAG_320_RC_INVAL_VCSSB_LEN 0x0202
20 +#define DIAG_320_RC_INVAL_VCB_LEN 0x0204
21 +#define DIAG_320_RC_BAD_RANGE 0x0302
22
23 #define DIAG_320_ISM_QUERY_SUBCODES 0x80000000
24 #define DIAG_320_ISM_QUERY_VCSI 0x40000000
25 +#define DIAG_320_ISM_STORE_VC 0x20000000
26
27 #define VCSSB_NO_VC 4
28 #define VCSSB_LEN_VALID 128
29
30 #define CERT_NAME_MAX_LEN 64
31
32 +/*
33 + * If the VCE flags indicate an invalid certificate,
34 + * the VCE length is set to 72, containing only the
35 + * first five fields of VCEntry.
36 + */
37 +#define VCE_INVALID_LEN 72
38 +
39 +#define DIAG_320_VCE_FLAGS_VALID 0x80
40 +
41 +typedef enum Diag320VceKeyType {
42 + DIAG_320_VCE_KEYTYPE_SELF_DESCRIBING = 0,
43 + DIAG_320_VCE_KEYTYPE_ECDSA_P521 = 1,
44 +} Diag320VceKeyType;
45 +
46 +typedef enum Diag320VceFormat {
47 + DIAG_320_VCE_FORMAT_X509_DER = 1,
48 +} Diag320VceFormat;
49 +
50 +typedef enum Diag320VceHashType {
51 + DIAG_320_VCE_HASHTYPE_SHA2_256 = 1,
52 +} Diag320VceHashType;
53 +
54 struct VCStorageSizeBlock {
55 uint32_t length;
56 uint8_t reserved0[3];
@@ -60,6 +86,12 @@ struct VCEntryHeader {
86 };
87 typedef struct VCEntryHeader VCEntryHeader;
88
89 +struct VCEntry {
90 + VCEntryHeader vce_hdr;
91 + uint8_t cert_buf[];
92 +};
93 +typedef struct VCEntry VCEntry;
94 +
95 struct VCBlockHeader {
96 uint32_t in_len;
97 uint32_t reserved0;
@@ -74,4 +106,10 @@ struct VCBlockHeader {
106 };
107 typedef struct VCBlockHeader VCBlockHeader;
108
109 +struct VCBlock {
110 + VCBlockHeader vcb_hdr;
111 + uint8_t vce_buf[];
112 +};
113 +typedef struct VCBlock VCBlock;
114 +
115 #endif
target/s390x/diag.c
+315 -1
@@ -17,13 +17,16 @@
17 #include "s390x-internal.h"
18 #include "hw/watchdog/wdt_diag288.h"
19 #include "system/cpus.h"
20 +#include "hw/s390x/cert-store.h"
21 #include "hw/s390x/ipl.h"
22 #include "hw/s390x/ipl/diag320.h"
23 #include "hw/s390x/s390-virtio-ccw.h"
24 #include "system/kvm.h"
25 #include "kvm/kvm_s390x.h"
26 #include "target/s390x/kvm/pv.h"
27 +#include "qapi/error.h"
28 #include "qemu/error-report.h"
29 +#include "crypto/x509-utils.h"
30
31
32 static inline bool diag_parm_addr_valid(uint64_t addr, size_t size, bool write)
@@ -241,8 +244,306 @@ static int handle_diag320_query_vcsi(S390CPU *cpu, uint64_t addr, uint64_t r1,
244 return DIAG_320_RC_OK;
245 }
246
247 +static bool is_cert_valid(const S390IPLCertificate *cert)
248 +{
249 + int rc;
250 + Error *err = NULL;
251 +
252 + rc = qcrypto_x509_check_cert_times(cert->raw, cert->size, &err);
253 + if (rc != 0) {
254 + error_report_err(err);
255 + return false;
256 + }
257 +
258 + return true;
259 +}
260 +
261 +static int handle_key_id(VCEntry *vce, const S390IPLCertificate *cert)
262 +{
263 + int rc;
264 + g_autofree unsigned char *key_id_data = NULL;
265 + size_t key_id_len;
266 + Error *err = NULL;
267 +
268 + rc = qcrypto_x509_get_cert_key_id(cert->raw, cert->size,
269 + QCRYPTO_HASH_ALGO_SHA256,
270 + &key_id_data, &key_id_len, &err);
271 + if (rc < 0) {
272 + error_report_err(err);
273 + return 0;
274 + }
275 +
276 + if (sizeof(VCEntryHeader) + key_id_len > be32_to_cpu(vce->vce_hdr.len)) {
277 + error_report("Unable to write key ID: exceeds buffer bounds");
278 + return 0;
279 + }
280 +
281 + vce->vce_hdr.keyid_len = cpu_to_be16(key_id_len);
282 +
283 + memcpy(vce->cert_buf, key_id_data, key_id_len);
284 +
285 + return ROUND_UP(key_id_len, 4);
286 +}
287 +
288 +static int handle_hash(VCEntry *vce, const S390IPLCertificate *cert,
289 + uint16_t keyid_field_len)
290 +{
291 + int rc;
292 + uint16_t hash_offset;
293 + g_autofree void *hash_data = NULL;
294 + size_t hash_len;
295 + Error *err = NULL;
296 +
297 + hash_len = CERT_HASH_LEN;
298 + hash_data = g_malloc0(hash_len);
299 + rc = qcrypto_get_x509_cert_fingerprint(cert->raw, cert->size,
300 + QCRYPTO_HASH_ALGO_SHA256,
301 + hash_data, &hash_len, &err);
302 + if (rc < 0) {
303 + error_report_err(err);
304 + return 0;
305 + }
306 +
307 + hash_offset = sizeof(VCEntryHeader) + keyid_field_len;
308 + if (hash_offset + hash_len > be32_to_cpu(vce->vce_hdr.len)) {
309 + error_report("Unable to write hash: exceeds buffer bounds");
310 + return 0;
311 + }
312 +
313 + vce->vce_hdr.hash_len = cpu_to_be16(hash_len);
314 + vce->vce_hdr.hash_type = DIAG_320_VCE_HASHTYPE_SHA2_256;
315 + vce->vce_hdr.hash_offset = cpu_to_be16(hash_offset);
316 +
317 + memcpy((uint8_t *)vce + hash_offset, hash_data, hash_len);
318 +
319 + return ROUND_UP(hash_len, 4);
320 +}
321 +
322 +static int handle_cert(VCEntry *vce, const S390IPLCertificate *cert,
323 + uint16_t hash_field_len)
324 +{
325 + int rc;
326 + uint16_t cert_offset;
327 + g_autofree uint8_t *cert_der = NULL;
328 + size_t der_size;
329 + Error *err = NULL;
330 +
331 + rc = qcrypto_x509_convert_cert_der(cert->raw, cert->size,
332 + &cert_der, &der_size, &err);
333 + if (rc < 0) {
334 + error_report_err(err);
335 + return 0;
336 + }
337 +
338 + cert_offset = be16_to_cpu(vce->vce_hdr.hash_offset) + hash_field_len;
339 + if (cert_offset + der_size > be32_to_cpu(vce->vce_hdr.len)) {
340 + error_report("Unable to write certificate: exceeds buffer bounds");
341 + return 0;
342 + }
343 +
344 + vce->vce_hdr.format = DIAG_320_VCE_FORMAT_X509_DER;
345 + vce->vce_hdr.cert_len = cpu_to_be32(der_size);
346 + vce->vce_hdr.cert_offset = cpu_to_be16(cert_offset);
347 +
348 + memcpy((uint8_t *)vce + cert_offset, cert_der, der_size);
349 +
350 + return ROUND_UP(der_size, 4);
351 +}
352 +
353 +static int get_key_type(const S390IPLCertificate *cert)
354 +{
355 + int rc;
356 + Error *err = NULL;
357 +
358 + rc = qcrypto_x509_check_ecc_curve_p521(cert->raw, cert->size, &err);
359 + if (rc == -1) {
360 + error_report_err(err);
361 + return -1;
362 + }
363 +
364 + return (rc == 1) ? DIAG_320_VCE_KEYTYPE_ECDSA_P521 :
365 + DIAG_320_VCE_KEYTYPE_SELF_DESCRIBING;
366 +}
367 +
368 +static int build_vce_header(VCEntry *vce, const S390IPLCertificate *cert, int idx)
369 +{
370 + int key_type;
371 +
372 + vce->vce_hdr.len = cpu_to_be32(sizeof(VCEntryHeader));
373 + vce->vce_hdr.cert_idx = cpu_to_be16(idx + 1);
374 + memcpy(vce->vce_hdr.name, cert->name, CERT_NAME_MAX_LEN);
375 +
376 + if (!is_cert_valid(cert)) {
377 + return -1;
378 + }
379 +
380 + key_type = get_key_type(cert);
381 + if (key_type == -1) {
382 + return -1;
383 + }
384 + vce->vce_hdr.key_type = key_type;
385 +
386 + return 0;
387 +}
388 +
389 +static int build_vce_data(VCEntry *vce, const S390IPLCertificate *cert,
390 + uint32_t vce_max_len)
391 +{
392 + uint16_t keyid_field_len;
393 + uint16_t hash_field_len;
394 + uint32_t cert_field_len;
395 + uint32_t vce_len;
396 +
397 + vce->vce_hdr.len = cpu_to_be32(vce_max_len);
398 +
399 + keyid_field_len = handle_key_id(vce, cert);
400 + if (!keyid_field_len) {
401 + return -1;
402 + }
403 +
404 + hash_field_len = handle_hash(vce, cert, keyid_field_len);
405 + if (!hash_field_len) {
406 + return -1;
407 + }
408 +
409 + cert_field_len = handle_cert(vce, cert, hash_field_len);
410 + if (!cert_field_len) {
411 + return -1;
412 + }
413 +
414 + vce_len = sizeof(VCEntryHeader) + keyid_field_len + hash_field_len + cert_field_len;
415 + if (vce_len > vce_max_len) {
416 + return -1;
417 + }
418 +
419 + vce->vce_hdr.flags |= DIAG_320_VCE_FLAGS_VALID;
420 +
421 + /* Update vce length to reflect the actual size used by vce */
422 + vce->vce_hdr.len = cpu_to_be32(vce_len);
423 +
424 + return 0;
425 +}
426 +
427 +static int handle_diag320_store_vc(S390CPU *cpu, uint64_t addr, uint64_t r1, uintptr_t ra,
428 + S390IPLCertificateStore *cs)
429 +{
430 + g_autofree VCBlockHeader *vcb_hdr = NULL;
431 + size_t remaining_space;
432 + uint16_t first_vc_index;
433 + uint16_t last_vc_index;
434 + int cs_start_index;
435 + int cs_end_index;
436 + uint32_t vce_max_len;
437 + uint32_t vce_len;
438 + uint32_t in_len;
439 +
440 + vcb_hdr = g_new0(VCBlockHeader, 1);
441 + if (s390_cpu_virt_mem_read(cpu, addr, r1, vcb_hdr, sizeof(*vcb_hdr))) {
442 + s390_cpu_virt_mem_handle_exc(cpu, ra);
443 + return -1;
444 + }
445 +
446 + in_len = be32_to_cpu(vcb_hdr->in_len);
447 + first_vc_index = be16_to_cpu(vcb_hdr->first_vc_index);
448 + last_vc_index = be16_to_cpu(vcb_hdr->last_vc_index);
449 +
450 + if (in_len % TARGET_PAGE_SIZE != 0) {
451 + return DIAG_320_RC_INVAL_VCB_LEN;
452 + }
453 +
454 + if (first_vc_index > last_vc_index) {
455 + return DIAG_320_RC_BAD_RANGE;
456 + }
457 +
458 + vcb_hdr->out_len = sizeof(VCBlockHeader);
459 +
460 + /*
461 + * DIAG 320 subcode 2 expects to query a certificate store that
462 + * maintains an index origin of 1. However, the S390IPLCertificateStore
463 + * maintains an index origin of 0. Thus, the indices must be adjusted
464 + * for correct access into the cert store. A couple of special cases
465 + * must also be accounted for.
466 + */
467 +
468 + /* Both indices are 0; return header with no certs */
469 + if (first_vc_index == 0 && last_vc_index == 0) {
470 + goto out;
471 + }
472 +
473 + /* Normalize indices */
474 + cs_start_index = (first_vc_index == 0) ? 0 : first_vc_index - 1;
475 + cs_end_index = last_vc_index - 1;
476 +
477 + /* Requested range is outside the cert store; return header with no certs */
478 + if (cs_start_index >= cs->count || cs_end_index >= cs->count) {
479 + goto out;
480 + }
481 +
482 + remaining_space = in_len - sizeof(VCBlockHeader);
483 +
484 + for (int i = cs_start_index; i <= cs_end_index; i++) {
485 + const S390IPLCertificate *cert = &cs->certs[i];
486 + /*
487 + * Each field of the VCE is word-aligned.
488 + * Allocate enough space for the largest possible size for this VCE.
489 + * As the certificate fields (key-id, hash, data) are parsed, the
490 + * VCE's length field will be updated accordingly.
491 + */
492 + vce_max_len = sizeof(VCEntryHeader) + ROUND_UP(CERT_KEY_ID_LEN, 4) +
493 + ROUND_UP(CERT_HASH_LEN, 4) + ROUND_UP(cert->der_size, 4);
494 + g_autofree VCEntry *vce = g_malloc0(vce_max_len);
495 +
496 + /*
497 + * Bit 0 of the VCE flags indicates whether the certificate is valid.
498 + * The caller of DIAG320 subcode 2 is responsible for verifying that
499 + * the VCE contains a valid certificate.
500 + */
501 + if (build_vce_header(vce, cert, i) || build_vce_data(vce, cert, vce_max_len)) {
502 + /*
503 + * Error occurs - VCE does not contain a valid certificate.
504 + * Bit 0 of the VCE flags is 0 and the VCE length is set.
505 + */
506 + vce->vce_hdr.len = cpu_to_be32(VCE_INVALID_LEN);
507 + }
508 + vce_len = be32_to_cpu(vce->vce_hdr.len);
509 +
510 + /*
511 + * If there is no more space to store the cert,
512 + * set the remaining verification cert count and
513 + * break early.
514 + */
515 + if (remaining_space < vce_len) {
516 + vcb_hdr->remain_ct = cpu_to_be16(last_vc_index - i);
517 + break;
518 + }
519 +
520 + /* Write VCE */
521 + if (s390_cpu_virt_mem_write(cpu, addr + vcb_hdr->out_len, r1, vce, vce_len)) {
522 + s390_cpu_virt_mem_handle_exc(cpu, ra);
523 + return -1;
524 + }
525 +
526 + vcb_hdr->out_len += vce_len;
527 + remaining_space -= vce_len;
528 + vcb_hdr->stored_ct++;
529 + }
530 + vcb_hdr->stored_ct = cpu_to_be16(vcb_hdr->stored_ct);
531 +
532 +out:
533 + vcb_hdr->out_len = cpu_to_be32(vcb_hdr->out_len);
534 +
535 + if (s390_cpu_virt_mem_write(cpu, addr, r1, vcb_hdr, sizeof(VCBlockHeader))) {
536 + s390_cpu_virt_mem_handle_exc(cpu, ra);
537 + return -1;
538 + }
539 +
540 + return DIAG_320_RC_OK;
541 +}
542 +
543 QEMU_BUILD_BUG_MSG(sizeof(VCStorageSizeBlock) != VCSSB_LEN_VALID,
544 "size of VCStorageSizeBlock is wrong");
545 +QEMU_BUILD_BUG_MSG(sizeof(VCBlock) != 64, "size of VCBlock is wrong");
546 +QEMU_BUILD_BUG_MSG(sizeof(VCEntry) != 128, "size of VCEntry is wrong");
547
548 void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
549 {
@@ -273,7 +574,8 @@ void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
574 * for now.
575 */
576 ism_word0 = cpu_to_be32(DIAG_320_ISM_QUERY_SUBCODES |
276 - DIAG_320_ISM_QUERY_VCSI);
577 + DIAG_320_ISM_QUERY_VCSI |
578 + DIAG_320_ISM_STORE_VC);
579
580 if (s390_cpu_virt_mem_write(cpu, addr, r1, &ism_word0, sizeof(ism_word0))) {
581 s390_cpu_virt_mem_handle_exc(cpu, ra);
@@ -299,6 +601,18 @@ void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
601 }
602 env->regs[r1 + 1] = rc;
603 break;
604 + case DIAG_320_SUBC_STORE_VC:
605 + if (addr & ~TARGET_PAGE_MASK) {
606 + s390_program_interrupt(env, PGM_SPECIFICATION, ra);
607 + return;
608 + }
609 +
610 + rc = handle_diag320_store_vc(cpu, addr, r1, ra, cs);
611 + if (rc == -1) {
612 + return;
613 + }
614 + env->regs[r1 + 1] = rc;
615 + break;
616 default:
617 env->regs[r1 + 1] = DIAG_320_RC_NOT_SUPPORTED;
618 break;