target/arm: Introduce cpu types max-v8 and max-v9
Introduce the names and allow them with the virt and sbsa-ref machine types. So far, the cpu types both exactly match "max". Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260827041557.775080-5-richard.henderson@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 21:15 UTC
717b67ac3ecd9b92b78ae7bb67cd9b9e78050550
4 files changed
+16
hw/arm/sbsa-ref.c
+2
@@ -913,6 +913,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, const void *data)
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ARM_CPU_TYPE_NAME("neoverse-v1"),
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ARM_CPU_TYPE_NAME("neoverse-n2"),
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ARM_CPU_TYPE_NAME("max"),
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+ ARM_CPU_TYPE_NAME("max-v8"),
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+ ARM_CPU_TYPE_NAME("max-v9"),
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NULL,
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};
920
hw/arm/virt.c
+2
@@ -4132,6 +4132,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
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if (tcg_enabled()) {
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
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+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8")));
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}
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if (tcg_enabled() && target_aarch64()) {
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
@@ -4143,6 +4144,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
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+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9")));
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}
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if (target_aarch64()) {
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g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
target/arm/tcg/cpu-max-v8.c
+11
@@ -2,6 +2,7 @@
2
3
#include "qemu/osdep.h"
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#include "cpu.h"
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+#include "qemu/target-info.h"
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#include "internals.h"
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8
@@ -117,3 +118,13 @@ void aarch32_max_v8_tcg_initfn(Object *obj)
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cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
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#endif
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}
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+
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+static void cpu_max_v8_register_type(void)
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+{
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+ static const ARMCPUInfo max_v8[2] = {
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+ { .name = "max-v8", .initfn = aarch32_max_v8_tcg_initfn },
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+ { .name = "max-v8", .initfn = aarch64_max_tcg_initfn }
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+ };
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+ arm_cpu_register(&max_v8[target_aarch64()]);
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+}
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+type_init(cpu_max_v8_register_type)
target/arm/tcg/cpu64.c
+1
@@ -1488,6 +1488,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
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{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
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{ .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
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{ .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
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+ { .name = "max-v9", .initfn = aarch64_max_tcg_initfn },
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};
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static void aarch64_cpu_register_types(void)