@samitouri / QOSamiQemu / commits / 72b4174d2f

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

Register machines able to run in qemu-system-riscv32, qemu-system-riscv64, or both. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-4-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Anton Johansson committed Apr 30, 2025 at 14:16 UTC 72b4174d2f47c770aaa87b8dedfcc65082d8e3a7

10 files changed +21 -2

hw/riscv/boston-aia.c

+2 -1

@@ -18,6 +18,7 @@

18 #include "hw/ide/ahci-pci.h"

19 #include "hw/core/loader.h"

20 #include "hw/riscv/cps.h"

21 +#include "hw/riscv/machines-qom.h"

22 #include "hw/pci-host/xilinx-pcie.h"

23 #include "hw/core/qdev-properties.h"

24 #include "qapi/error.h"

@@ -473,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc)

474 mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700;

475 }

476

476 -DEFINE_MACHINE("boston-aia", boston_mach_class_init)

477 +DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init)

hw/riscv/microblaze-v-generic.c

+2 -1

@@ -25,6 +25,7 @@

25 #include "system/address-spaces.h"

26 #include "hw/char/xilinx_uartlite.h"

27 #include "hw/misc/unimp.h"

28 +#include "hw/riscv/machines-qom.h"

30 #define LMB_BRAM_SIZE (128 * KiB)

31 #define MEMORY_BASEADDR 0x80000000

@@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc)

187 mc->default_cpus = 1;

188 }

189

189 -DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)

190 +DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init)

hw/riscv/microchip_pfsoc.c

@@ -49,6 +49,7 @@

49 #include "hw/misc/unimp.h"

50 #include "hw/riscv/boot.h"

51 #include "hw/riscv/riscv_hart.h"

52 +#include "hw/riscv/machines-qom.h"

53 #include "hw/riscv/microchip_pfsoc.h"

54 #include "hw/intc/riscv_aclint.h"

55 #include "hw/intc/sifive_plic.h"

@@ -751,6 +752,7 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {

752 .class_init = microchip_icicle_kit_machine_class_init,

753 .instance_init = microchip_icicle_kit_machine_instance_init,

754 .instance_size = sizeof(MicrochipIcicleKitState),

755 + .interfaces = riscv64_machine_interfaces,

756 };

757

758 static void microchip_icicle_kit_machine_init_register_types(void)

hw/riscv/opentitan.c

@@ -26,6 +26,7 @@

26 #include "hw/core/boards.h"

27 #include "hw/misc/unimp.h"

28 #include "hw/riscv/boot.h"

29 +#include "hw/riscv/machines-qom.h"

30 #include "qemu/units.h"

31 #include "system/system.h"

32 #include "system/address-spaces.h"

@@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] = {

336 .parent = TYPE_MACHINE,

337 .instance_size = sizeof(OpenTitanState),

338 .class_init = opentitan_machine_class_init,

339 + .interfaces = riscv32_machine_interfaces,

340 }

341 };

342

hw/riscv/shakti_c.c

@@ -19,6 +19,7 @@

19 #include "qemu/osdep.h"

20 #include "hw/core/boards.h"

21 #include "hw/riscv/shakti_c.h"

22 +#include "hw/riscv/machines-qom.h"

23 #include "qapi/error.h"

24 #include "qemu/error-report.h"

25 #include "hw/intc/sifive_plic.h"

@@ -93,6 +94,7 @@ static const TypeInfo shakti_c_machine_type_info = {

94 .class_init = shakti_c_machine_class_init,

95 .instance_init = shakti_c_machine_instance_init,

96 .instance_size = sizeof(ShaktiCMachineState),

97 + .interfaces = riscv64_machine_interfaces,

98 };

100 static void shakti_c_machine_type_info_register(void)

hw/riscv/sifive_e.c

@@ -40,6 +40,7 @@

40 #include "hw/riscv/riscv_hart.h"

41 #include "hw/riscv/sifive_e.h"

42 #include "hw/riscv/boot.h"

43 +#include "hw/riscv/machines-qom.h"

44 #include "hw/char/sifive_uart.h"

45 #include "hw/intc/riscv_aclint.h"

46 #include "hw/intc/sifive_plic.h"

@@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo = {

168 .class_init = sifive_e_machine_class_init,

169 .instance_init = sifive_e_machine_instance_init,

170 .instance_size = sizeof(SiFiveEState),

171 + .interfaces = riscv32_64_machine_interfaces,

172 };

173

174 static void sifive_e_machine_init_register_types(void)

hw/riscv/sifive_u.c

@@ -51,6 +51,7 @@

51 #include "hw/riscv/riscv_hart.h"

52 #include "hw/riscv/sifive_u.h"

53 #include "hw/riscv/boot.h"

54 +#include "hw/riscv/machines-qom.h"

55 #include "hw/char/sifive_uart.h"

56 #include "hw/intc/riscv_aclint.h"

57 #include "hw/intc/sifive_plic.h"

@@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo = {

743 .class_init = sifive_u_machine_class_init,

744 .instance_init = sifive_u_machine_instance_init,

745 .instance_size = sizeof(SiFiveUState),

746 + .interfaces = riscv32_64_machine_interfaces,

747 };

748

749 static void sifive_u_machine_init_register_types(void)

hw/riscv/spike.c

@@ -33,6 +33,7 @@

33 #include "hw/riscv/spike.h"

34 #include "hw/riscv/boot.h"

35 #include "hw/riscv/numa.h"

36 +#include "hw/riscv/machines-qom.h"

37 #include "hw/char/riscv_htif.h"

38 #include "hw/intc/riscv_aclint.h"

39 #include "chardev/char.h"

@@ -365,6 +366,7 @@ static const TypeInfo spike_machine_typeinfo = {

366 .class_init = spike_machine_class_init,

367 .instance_init = spike_machine_instance_init,

368 .instance_size = sizeof(SpikeState),

369 + .interfaces = riscv32_64_machine_interfaces,

370 };

371

372 static void spike_machine_init_register_types(void)

hw/riscv/virt.c

@@ -36,6 +36,7 @@

36 #include "hw/riscv/riscv-iommu-bits.h"

37 #include "hw/riscv/virt.h"

38 #include "hw/riscv/boot.h"

39 +#include "hw/riscv/machines-qom.h"

40 #include "hw/riscv/numa.h"

41 #include "kvm/kvm_riscv.h"

42 #include "hw/firmware/smbios.h"

@@ -2001,6 +2002,8 @@ static const TypeInfo virt_machine_typeinfo = {

2002 .instance_size = sizeof(RISCVVirtState),

2003 .interfaces = (const InterfaceInfo[]) {

2004 { TYPE_HOTPLUG_HANDLER },

2005 + { TYPE_TARGET_RISCV32_MACHINE },

2006 + { TYPE_TARGET_RISCV64_MACHINE },

2007 { }

2008 },

2009 };

hw/riscv/xiangshan_kmh.c

@@ -41,6 +41,7 @@

41 #include "hw/riscv/boot.h"

42 #include "hw/riscv/xiangshan_kmh.h"

43 #include "hw/riscv/riscv_hart.h"

44 +#include "hw/riscv/machines-qom.h"

45 #include "system/system.h"

47 static const MemMapEntry xiangshan_kmh_memmap[] = {

@@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info = {

212 .parent = TYPE_MACHINE,

213 .instance_size = sizeof(XiangshanKmhState),

214 .class_init = xiangshan_kmh_machine_class_init,

215 + .interfaces = riscv64_machine_interfaces,

216 };

217

218 static void xiangshan_kmh_machine_register_types(void)