target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S
PPC2_ISA207S is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ISA207S could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-35-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
735ebef6e77e563c0b6bb6e968de801103583062
10 files changed
+19
-23
hw/ppc/spapr_caps.c
+1
-1
@@ -676,7 +676,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
676
677
if (tcg_enabled()) {
678
/* AIL-3 is only supported on POWER8 and above CPUs. */
679
- if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
679
+ if (!(pcc->insns_flags2 & PPC2_ISA207)) {
680
error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs");
681
error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n");
682
return;
linux-user/ppc/elfload.c
+1
-1
@@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
116
do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
117
118
GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
119
- GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
119
+ GET_FEATURE2(PPC2_ISA207, (QEMU_PPC_FEATURE2_ARCH_2_07 |
120
QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
121
GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
122
QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
target/ppc/cpu.h
+1
-4
@@ -2577,8 +2577,6 @@ enum {
2577
PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2578
/* ISA 2.06B floating point test instructions */
2579
PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2580
- /* PowerISA 2.07 Book3s specification */
2581
- PPC2_ISA207S = 0x0000000000008000ULL,
2580
/* Double precision floating point conversion for signed integer 64 */
2581
PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2582
/* Transactional Memory (ISA 2.07, Book II) */
@@ -2603,8 +2601,7 @@ enum {
2601
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2602
PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
2603
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2606
- PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2607
- PPC2_ISA207S | PPC2_DFP | \
2604
+ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_DFP | \
2605
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2606
PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2607
PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \
target/ppc/cpu_init.c
+1
-2
@@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
6349
pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
6350
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6351
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6352
- PPC2_FP_TST_ISA206 |
6353
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6352
+ PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_FP_CVT_S64 |
6353
PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6354
PPC2_BCDA_ISA206;
6355
pcc->msr_mask = (1ull << MSR_SF) |
target/ppc/cpu_init.h
+1
-1
@@ -18,7 +18,7 @@
18
(PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
19
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
20
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \
21
- PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
21
+ PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
22
PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
23
24
#define PPC_INSNS_FLAGS2_POWER9 \
target/ppc/tcg-excp_helper.c
+4
-4
@@ -314,7 +314,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs)
314
#if defined(TARGET_PPC64)
315
CPUPPCState *env = cpu_env(cs);
316
317
- if (env->insns_flags2 & PPC2_ISA207S) {
317
+ if (env->insns_flags2 & PPC2_ISA207) {
318
if (cs->watchpoint_hit) {
319
if (cs->watchpoint_hit->flags & BP_CPU) {
320
env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr;
@@ -336,7 +336,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
336
#if defined(TARGET_PPC64)
337
CPUPPCState *env = cpu_env(cs);
338
339
- if (env->insns_flags2 & PPC2_ISA207S) {
339
+ if (env->insns_flags2 & PPC2_ISA207) {
340
target_ulong priv;
341
342
priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63);
@@ -365,7 +365,7 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
365
bool wt, wti, hv, sv, pr;
366
uint32_t dawrx;
367
368
- if ((env->insns_flags2 & PPC2_ISA207S) &&
368
+ if ((env->insns_flags2 & PPC2_ISA207) &&
369
(wp == env->dawr_watchpoint[0])) {
370
dawrx = env->spr[SPR_DAWRX0];
371
} else if ((env->insns_flags2 & PPC2_ISA310) &&
@@ -849,7 +849,7 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
849
void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip)
850
{
851
uint32_t error_code = 0;
852
- if (env->insns_flags2 & PPC2_ISA207S) {
852
+ if (env->insns_flags2 & PPC2_ISA207) {
853
/* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */
854
env->spr[SPR_POWER_SIAR] = prev_ip;
855
error_code = PPC_BIT(33);
target/ppc/translate.c
+3
-3
@@ -2775,7 +2775,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
2775
}
2776
} else {
2777
/* ISA 2.07 defines these as no-ops */
2778
- if ((ctx->insns_flags2 & PPC2_ISA207S) &&
2778
+ if ((ctx->insns_flags2 & PPC2_ISA207) &&
2779
(sprn >= 808 && sprn <= 811)) {
2780
/* This is a nop */
2781
return;
@@ -2841,7 +2841,7 @@ static void gen_mtspr(DisasContext *ctx)
2841
}
2842
} else {
2843
/* ISA 2.07 defines these as no-ops */
2844
- if ((ctx->insns_flags2 & PPC2_ISA207S) &&
2844
+ if ((ctx->insns_flags2 & PPC2_ISA207) &&
2845
(sprn >= 808 && sprn <= 811)) {
2846
/* This is a nop */
2847
return;
@@ -4135,7 +4135,7 @@ TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ))
4135
static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a)
4136
{
4137
REQUIRE_64BIT(ctx);
4138
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
4138
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
4139
#if defined(TARGET_PPC64)
4140
TCGv EA;
4141
TCGv_i128 t16;
target/ppc/translate/bhrb-impl.c.inc
+2
-2
@@ -14,7 +14,7 @@
14
15
static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
16
{
17
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
17
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
18
TCGv_i32 bhrbe = tcg_constant_i32(arg->bhrbe);
19
gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe);
20
return true;
@@ -22,7 +22,7 @@ static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
22
23
static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg)
24
{
25
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
25
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
26
gen_helper_clrbhrb(tcg_env);
27
return true;
28
}
target/ppc/translate/branch-impl.c.inc
+1
-1
@@ -14,7 +14,7 @@
14
15
static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
16
{
17
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
17
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
18
19
translator_io_start(&ctx->base);
20
gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
target/ppc/translate/processor-ctrl-impl.c.inc
+4
-4
@@ -23,7 +23,7 @@
23
24
static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
25
{
26
- if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
26
+ if (!(ctx->insns_flags2 & PPC2_ISA207)) {
27
/*
28
* Before Power ISA 2.07, processor control instructions were only
29
* implemented in the "Embedded.Processor Control" category.
@@ -47,7 +47,7 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
47
48
static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
49
{
50
- if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
50
+ if (!(ctx->insns_flags2 & PPC2_ISA207)) {
51
/*
52
* Before Power ISA 2.07, processor control instructions were only
53
* implemented in the "Embedded.Processor Control" category.
@@ -72,7 +72,7 @@ static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
72
static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
73
{
74
REQUIRE_64BIT(ctx);
75
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
75
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
76
REQUIRE_SV(ctx);
77
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
78
gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
@@ -85,7 +85,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
85
static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
86
{
87
REQUIRE_64BIT(ctx);
88
- REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
88
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
89
REQUIRE_SV(ctx);
90
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
91
gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);