disas/riscv: Drop always true branch pseudos
The real insns are blt, bge, bltu, bgeu. Do not include pseudos that unconditionally swap operands. That's fine for an assembler but not a disassembler. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-22-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
7376e4d7d29c7c4bf4ad552624502c92e2deac06
1 file changed
+6
-26
disas/riscv.c
+6
-26
@@ -326,10 +326,6 @@ typedef enum {
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rv_op_bgez = 295,
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rv_op_bltz = 296,
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rv_op_bgtz = 297,
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- rv_op_ble = 298,
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- rv_op_bleu = 299,
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- rv_op_bgt = 300,
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- rv_op_bgtu = 301,
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rv_op_j = 302,
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rv_op_ret = 303,
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rv_op_jr = 304,
@@ -1062,10 +1058,6 @@ static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
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static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
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static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
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-static const rvc_constraint rvcc_ble[] = { rvc_end };
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-static const rvc_constraint rvcc_bleu[] = { rvc_end };
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-static const rvc_constraint rvcc_bgt[] = { rvc_end };
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-static const rvc_constraint rvcc_bgtu[] = { rvc_end };
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static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
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static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
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rvc_end };
@@ -1123,24 +1115,12 @@ static const rv_comp_data rvcp_bne[] = {
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static const rv_comp_data rvcp_blt[] = {
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{ rv_op_bltz, rvcc_bltz },
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{ rv_op_bgtz, rvcc_bgtz },
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- { rv_op_bgt, rvcc_bgt },
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{ rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_bge[] = {
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{ rv_op_blez, rvcc_blez },
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{ rv_op_bgez, rvcc_bgez },
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- { rv_op_ble, rvcc_ble },
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- { rv_op_illegal, NULL }
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-};
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-
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-static const rv_comp_data rvcp_bltu[] = {
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- { rv_op_bgtu, rvcc_bgtu },
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- { rv_op_illegal, NULL }
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-};
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-
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-static const rv_comp_data rvcp_bgeu[] = {
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- { rv_op_bleu, rvcc_bleu },
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{ rv_op_illegal, NULL }
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};
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@@ -1665,8 +1645,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
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{ "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
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{ "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
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{ "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
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- { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu },
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- { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu },
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+ { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
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+ { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
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{ "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
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{ "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
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{ "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
@@ -1954,10 +1934,10 @@ static const rv_opcode_data rvi_opcode_data[] = {
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{ "bgez", rv_codec_sb, rv_fmt_rs1_offset },
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{ "bltz", rv_codec_sb, rv_fmt_rs1_offset },
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{ "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
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- { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset },
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- { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
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- { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset },
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- { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
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+ { },
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+ { },
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+ { },
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+ { },
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{ "j", rv_codec_uj, rv_fmt_offset },
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{ "ret", rv_codec_i, rv_fmt_none },
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{ "jr", rv_codec_i, rv_fmt_rs1 },