configs/target: Implement per-binary TargetInfo structure for riscv
Defines TargetInfo for 32- and 64-bit riscv binaries. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-6-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Anton Johansson committed
Apr 30, 2025 at 14:17 UTC
750d25fc6615ff4db87bcf3a6b46e7266e59f5ae
3 files changed
+53
configs/targets/meson.build
+1
@@ -1,5 +1,6 @@
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foreach target : [
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'arm-softmmu', 'aarch64-softmmu',
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+ 'riscv32-softmmu', 'riscv64-softmmu'
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]
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config_target_info += {target : files(target + '.c')}
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endforeach
configs/targets/riscv32-softmmu.c
new
+26
@@ -0,0 +1,26 @@
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+/*
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+ * QEMU binary/target API (qemu-system-riscv32)
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+ *
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+ * Copyright (c) rev.ng Labs Srl.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/target-info-impl.h"
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+#include "qemu/target-info-init.h"
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+#include "hw/riscv/machines-qom.h"
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+#include "target/riscv/cpu-qom.h"
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+#include "target/riscv/cpu-param.h"
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+
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+static const TargetInfo target_info_riscv32_system = {
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+ .target_name = "riscv32",
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+ .target_arch = SYS_EMU_TARGET_RISCV32,
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+ .long_bits = 32,
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+ .cpu_type = TYPE_RISCV_CPU,
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+ .machine_typename = TYPE_TARGET_RISCV32_MACHINE,
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+ .endianness = ENDIAN_MODE_LITTLE,
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+ .page_bits_init = TARGET_PAGE_BITS,
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+};
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+
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+target_info_init(target_info_riscv32_system)
configs/targets/riscv64-softmmu.c
new
+26
@@ -0,0 +1,26 @@
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+/*
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+ * QEMU binary/target API (qemu-system-riscv64)
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+ *
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+ * Copyright (c) rev.ng Labs Srl.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/target-info-impl.h"
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+#include "qemu/target-info-init.h"
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+#include "hw/riscv/machines-qom.h"
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+#include "target/riscv/cpu-qom.h"
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+#include "target/riscv/cpu-param.h"
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+
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+static const TargetInfo target_info_riscv64_system = {
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+ .target_name = "riscv64",
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+ .target_arch = SYS_EMU_TARGET_RISCV64,
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+ .long_bits = 64,
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+ .cpu_type = TYPE_RISCV_CPU,
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+ .machine_typename = TYPE_TARGET_RISCV64_MACHINE,
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+ .endianness = ENDIAN_MODE_LITTLE,
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+ .page_bits_init = TARGET_PAGE_BITS,
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+};
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+
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+target_info_init(target_info_riscv64_system)