tests/qtest: add 8-byte MMIO access sweep for intel-iommu
Sweep every 4-byte-aligned offset in the VT-d MMIO register space with 8-byte reads and writes to verify that no register handler aborts on an oversized access. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Junjie Cao <junjie.cao@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260514180703.85686-3-junjie.cao@intel.com>
Junjie Cao committed
May 15, 2026 at 02:07 UTC
7578162c491c544fd76071964126cc53f3d82083
1 file changed
+30
tests/qtest/intel-iommu-test.c
+30
@@ -17,11 +17,39 @@
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#define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \
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VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FSTS)
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+static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset)
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+{
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+ return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
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+}
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+
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static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)
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{
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return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
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}
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+static inline void vtd_reg_writeq(QTestState *s, uint64_t offset,
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+ uint64_t value)
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+{
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+ qtest_writeq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset, value);
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+}
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+
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+static void test_intel_iommu_8byte_access(void)
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+{
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+ QTestState *s;
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+ uint64_t off;
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+
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+ s = qtest_init("-M q35 -device intel-iommu");
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+
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+ for (off = 0; off < DMAR_REG_SIZE; off += 4) {
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+ vtd_reg_readq(s, off);
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+ vtd_reg_writeq(s, off, 0);
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+ }
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+
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+ g_assert_cmpuint(vtd_reg_readl(s, DMAR_VER_REG), !=, 0);
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+
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+ qtest_quit(s);
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+}
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+
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static void test_intel_iommu_stage_1(void)
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{
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uint8_t init_csr[DMAR_REG_SIZE]; /* register values */
@@ -58,6 +86,8 @@ static void test_intel_iommu_stage_1(void)
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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+ qtest_add_func("/q35/intel-iommu/8byte-access",
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+ test_intel_iommu_8byte_access);
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qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1);
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return g_test_run();