@samitouri / QOSamiQemu / commits / 758dce9c98

disas/riscv.c: fix inst_length()

inst_length() can return 0 if 'inst' happens to not match any known encoding (like [1]). Returning 0 is not desirable, even for unknown encodings, given that it will cause a loop in target_disas() later on. The most recent version of the RISC-V unpriv spec ditched the sophisticated instruction-length encoding. We're now supporting only 16-bit and 32-bit length instructions, where: "All the 32-bit instructions in the base ISA have their lowest two bits set to 11. The optional compressed 16-bit instruction-set extensions have their lowest two bits equal to 00, 01, or 10." So the code is now simpler, never returning 0, and in fact it's the same thing we're already doing in insn_len() from target/riscv/internals.h. Due to include shenarigans we can't use that function in disas/riscv.c, but I believe we can cut ourselves some slack this time and not lose sleep over a 1 line of duplicated logic. We're documenting it though! [1] https://gitlab.com/qemu-project/qemu/-/work_items/3479 Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3479 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260527200355.2068879-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed May 27, 2026 at 17:03 UTC 758dce9c98af4f3ef26eada48a484a7d60258636
1 file changed +2 -18
disas/riscv.c
+2 -18
@@ -5084,26 +5084,10 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
5084 return true;
5085 }
5086
5087 -/* instruction length */
5088 -
5087 +/* Same as insn_len() from target/riscv/internals.h */
5088 static size_t inst_length(rv_inst inst)
5089 {
5091 - /* NOTE: supports maximum instruction size of 64-bits */
5092 -
5093 - /*
5094 - * instruction length coding
5095 - *
5096 - * aa - 16 bit aa != 11
5097 - * bbb11 - 32 bit bbb != 111
5098 - * 011111 - 48 bit
5099 - * 0111111 - 64 bit
5100 - */
5101 -
5102 - return (inst & 0b11) != 0b11 ? 2
5103 - : (inst & 0b11100) != 0b11100 ? 4
5104 - : (inst & 0b111111) == 0b011111 ? 6
5105 - : (inst & 0b1111111) == 0b0111111 ? 8
5106 - : 0;
5090 + return (inst & 3) == 3 ? 4 : 2;
5091 }
5092
5093 /* format instruction */