target/arm: Split vector-type.h from cpu.h
We want to be able to reference ARMVectorType etc from common code, so move it out of cpu.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
784b01c77dcec5ffb9284d119dc19abdb91c38f2
2 files changed
+45
-37
target/arm/cpu.h
+1
-37
@@ -35,6 +35,7 @@
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#include "target/arm/cpu-sysregs.h"
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#include "target/arm/mmuidx.h"
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#include "hw/intc/arm_gicv5_types.h"
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+#include "target/arm/vector-type.h"
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_SWI 2 /* software interrupt */
@@ -140,43 +141,6 @@ typedef struct ARMGenericTimer {
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uint64_t ctl; /* Timer Control register */
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} ARMGenericTimer;
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-/* Define a maximum sized vector register.
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- * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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- * For 64-bit, this is a 2048-bit SVE register.
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- *
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- * Note that the mapping between S, D, and Q views of the register bank
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- * differs between AArch64 and AArch32.
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- * In AArch32:
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- * Qn = regs[n].d[1]:regs[n].d[0]
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- * Dn = regs[n / 2].d[n & 1]
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- * Sn = regs[n / 4].d[n % 4 / 2],
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- * bits 31..0 for even n, and bits 63..32 for odd n
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- * (and regs[16] to regs[31] are inaccessible)
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- * In AArch64:
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- * Zn = regs[n].d[*]
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- * Qn = regs[n].d[1]:regs[n].d[0]
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- * Dn = regs[n].d[0]
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- * Sn = regs[n].d[0] bits 31..0
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- * Hn = regs[n].d[0] bits 15..0
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- *
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- * This corresponds to the architecturally defined mapping between
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- * the two execution states, and means we do not need to explicitly
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- * map these registers when changing states.
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- *
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- * Align the data for use with TCG host vector operations.
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- */
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-
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-#define ARM_MAX_VQ 16
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-
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-typedef struct ARMVectorReg {
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- uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
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-} ARMVectorReg;
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-
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-/* In AArch32 mode, predicate registers do not exist at all. */
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-typedef struct ARMPredicateReg {
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- uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
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-} ARMPredicateReg;
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-
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/* In AArch32 mode, PAC keys do not exist at all. */
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typedef struct ARMPACKey {
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uint64_t lo, hi;
target/arm/vector-type.h
new
+44
@@ -0,0 +1,44 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+#ifndef TARGET_ARM_VECTOR_TYPE_H
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+#define TARGET_ARM_VECTOR_TYPE_H
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+
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+/*
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+ * Define a maximum sized vector register.
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+ * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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+ * For 64-bit, this is a 2048-bit SVE register.
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+ *
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+ * Note that the mapping between S, D, and Q views of the register bank
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+ * differs between AArch64 and AArch32.
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+ * In AArch32:
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+ * Qn = regs[n].d[1]:regs[n].d[0]
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+ * Dn = regs[n / 2].d[n & 1]
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+ * Sn = regs[n / 4].d[n % 4 / 2],
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+ * bits 31..0 for even n, and bits 63..32 for odd n
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+ * (and regs[16] to regs[31] are inaccessible)
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+ * In AArch64:
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+ * Zn = regs[n].d[*]
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+ * Qn = regs[n].d[1]:regs[n].d[0]
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+ * Dn = regs[n].d[0]
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+ * Sn = regs[n].d[0] bits 31..0
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+ * Hn = regs[n].d[0] bits 15..0
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+ *
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+ * This corresponds to the architecturally defined mapping between
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+ * the two execution states, and means we do not need to explicitly
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+ * map these registers when changing states.
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+ *
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+ * Align the data for use with TCG host vector operations.
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+ */
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+
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+#define ARM_MAX_VQ 16
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+
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+typedef struct ARMVectorReg {
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+ uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
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+} ARMVectorReg;
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+
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+/* In AArch32 mode, predicate registers do not exist at all. */
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+typedef struct ARMPredicateReg {
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+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
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+} ARMPredicateReg;
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+
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+#endif