target/arm: Don't provide TLBTR for pre-v6 CPUs

The TLBTR register (encoding cp15, 0, c0, c0, 3) is listed in the v7A Arm ARM appendix O as being present in v4 and v5 (section O.7.1, diagram "Organization of CP15 registers in an ARMv4 or ARMv5 VMSA implementation"). However, it isn't listed in the v5 Arm ARM, and checking individual TRMs for the arm926, arm1026, sa1100, sa1110 and ti925 shows that none of them implement it, so it seems much more likely that TLBTR was new for v6. It's also confirmed not to be present on a real arm926. Gate the register on ARM_FEATURE_V6 being present; this means that on pre-v6 cores the encoding will fall back to reporting the MIDR (due to the CP_ANY wildcarding), matching the hardware behaviour. We can also remove the "make id_tlbtr_reginfo r/w for strongarm and omap" code, because those CPUs are pre-v6 so won't be using that reginfo struct now. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4207 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260821120036.4161792-1-peter.maydell@linaro.org