@samitouri / QOSamiQemu / commits / 7899d3c6bd

disas/riscv: Use signed type for vector immediates

operand_vimm() sign-extends the 5-bit vector immediate field in bits 19:15, but returns uint32_t. This sends negative immediates through an unsigned type before they are assigned to rv_decode.imm. Return int32_t to match the signed value extracted by the helper. Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703-b4-disas-xthead-fix-riscv-next-v4-3-84c566330bc7@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

TANG Tiancheng committed Jul 3, 2026 at 13:03 UTC 7899d3c6bdb008dd301b474f3524bad5f37a411e
1 file changed +1 -1
disas/riscv.c
+1 -1
@@ -4487,7 +4487,7 @@ static uint32_t operand_cimmq(rv_inst inst)
4487 ((inst << 57) >> 62) << 6;
4488 }
4489
4490 -static uint32_t operand_vimm(rv_inst inst)
4490 +static int32_t operand_vimm(rv_inst inst)
4491 {
4492 return (int64_t)(inst << 44) >> 59;
4493 }